Download ECE 352 Electronics II

Transistor - Transistor Logic (TTL)
iR
iC3
vi
ECES 352 Winter 2007
*
TTL basics of operation
 Similar to that of simplified TTL
 Why Q2 and Q4 added?
 Why the diode D added?
*
For input low,
 Current iR flows out the input (E of Q1)
into the output of inverter driving input.
 Q2 is in cutoff since it gets no base
current from Q1.
 Q3 is in cutoff since it gets no base
current from Q2.
 Output is high since iC3 ≈ 0.
*
For input high,
 Current iR flows out C of Q1 into base of
Q2.
 Q2 comes on in active mode and then
moves into saturation.
 Q2’s emitter current provides base current
for Q3.
 Q3 comes on in active and then moves
into saturation mode so output goes low,
i.e. vo ≈ VCE,sat = 0.2V.
vo
Ch 11 Bipolar Digital Pt. 3
1
Transistor - Transistor Logic (TTL)
*
Assumptions for analysis:




vo
vi

ECES 352 Winter 2007
All transistors are npn and identical.
For p-n junctions in transistors to be
conducting current,
 VBE or VBC must be 0.7V or higher.
 For smaller junction voltages, current
flow is negligibly small.
For transistors in forward active mode,
 iC = β iB,
 VBE,active ≈ 0.7 V
For transistors in forward saturation mode,
 VBE,sat ≈ 0.8 V.
 VCE,sat ≈ 0.2 V.
 iC < β iB or iC / iB < β.
For transistors in inverse mode (E junction
reverse biased, C junction forward biased),
 current gain is very small
 iE = βr iB
 βr is very small, e.g. βr ~ 0.02
Ch 11 Bipolar Digital Pt. 3
2
Transistor - Transistor Logic (TTL)
Low Input, High Output
*
For input low, i.e. vi = 0.2 V
 Current iR = iRi flows out E of Q1 into
inverter driving the input.
VB1  vi  VBE1  0.2 V  0.7 V  0.9 V
iRi  VCC  VB1  / R  5 V  0.9 V / 4K  1.0 mA
iRi

VB1

+ + VBC1
VBE1
_
_
+
vi =VCE,sat
= 0.2V
_
+
VBE2 _
Cutoff
iC3
+ _
VBE3

vo
Q2 is in cutoff since it gets almost no
base current.
Q3 is in cutoff since it gets no base
current from Q2.
Why?
VB1  VBC1  VBE 2  VBE 3  0.9 V
0.9V
 0.3 V
3
Since 0.3 V  0.7 V , so the junctions
so VBC1  VBE 2  VBE 3 
Cutoff
are not conducting any sizable current.

ECES 352 Winter 2007
Output is high since iC3 ≈ 0 since Q3 is
off.
Ch 11 Bipolar Digital Pt. 3
3
Transistor - Transistor Logic (TTL)
Low Input, High Output
*
VCC = 5 V
iR1
iRi
R1 =
1.6 K
VB1
VBE1
_
+ + VBC1
_
+
vi =VCE,sat
= 0.2V
_
iC2
R3 =
0.13 K
iB4
weakly on
+
VBE4 _
+ _ off
VBE2
iD
+ _
VBE3
+V
_ D
io
p
For input low, i.e. vi = 0.2 V
 Output is high since iC3 ≈ 0
since Q3 is off.
 What is the high output
voltage? VCC?
 Look at Q4 and diode D.
 Since Q2 is off, iC2 ≈ 0 and so
iB4 ≈ iR1
 Then we can write
vo  VCC  iR1R1  VBE 4  VD
n
+
_ vo = HIGH
 5 V  iR1R1  0.7V  0.7V  3.6V  iR1R1


off


How big is iB4 ≈ iR1?
Since Q3 is off, iC3 ≈ 0 and so
iR1 ≈ iB4 ≈ iD ≈ i0 .
For the output high, the next
inverter will have its Q1’s
emitter junction reverse biased
so i0 ≈ iE1 ≈ 0.
So iB4 ≈ 0, VBE4 ≈ VD = 0.65 V so
vo  VCC  VBE 4  VD  iR1R1
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 3
 5 V  0.65 V  0.65 V  3.7 V 4
Transistor - Transistor Logic (TTL)
Low Input, High Output
*
iRi
R1 =
1.6 K
VB1
VBE1
_
+ + VBC1
_
+
vi =VCE,sat
= 0.2V
_
iC2
+
VBE2 _
In summary, for input low, i.e. vi = 0.2 V
VCC = 5 V  E junction of Q1 forward biased, so
most of iR flows out of E into
collector of driving inverter.
iR1
 The voltage at the base of Q1 is
R3 =
low, only 0.2 V + 0.7 V = 0.9 V, so the
0.13 K
bias for the three junctions in series
iB4
weakly on
is only 0.9 V so VBC1 ≈ VBE2 ≈ VBE3 ≈
+ _
0.3 V, which are too low to conduct.
VBE4
+V
 So Q2 and Q3 are in cutoff.
p
_ D io ≈ 0
n
 Since output is high and connected
off
+
to a reverse biased E junction for
v
=
3.7
high
V
Q1 for the following inverter io ≈ 0
_o
off
 So iB4 ≈ 0, Q4 and D are weakly on
+ _
so VBE4 ≈ VD = 0.65 V.
VBE3
 Very little current is draw by
output.
 The output voltage is high.
vo  VCC  VBE 4  VD  iR1R1
 5 V  0.65 V  0.65 V  3.7 V
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 3
5
Transistor - Transistor Logic (TTL)
High Input, Low Output
*
VCC = 5 V
iR1
iRi
R1 =
1.6 K
VB1
+ + VBC1
VBE1
_
_
iC2
+
iB2 +
vi = iE1 ≈ 0
VBE2 _
3.7V
_
R3 =
0.13 K
iB4
+
VBE4 _
+V
_ D
on
iE2
+
vo
_
iB3
+ _
VBE3
io
p
For input high, i.e. vi = 3.7 V
 Output is low since Q2 and Q3
are on. vo = ?
 Since input is high, iE1 ≈ 0 so
iC1 ≈ iB2 ≈ iRi.
 Then
VB1  VBC1  VBE 2  VBE3
 Since there is current flow out
C of Q1 into base of Q2 and
then into base of Q3, then
VBC1  VBE 2  VBE3  0.7 V so
n
VB1  3(0.7 V )  2.1 V and so
VBE1  VB1  vi  2.1 V  3.7 V  1.6 V
low
so Q1 E jcn. is reverse biased as assumed.
on

Then
iRi 
iR2

But the base currents for Q2 and Q3 are very large
and drive these transistors well into saturation.
Q2 cannot be in active mode since
ic2R1 = (7.3 mA)(1.6K) = 11.7 V >> VCC!
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 3
VCC  VB1 5 V  2.1 V

 0.73 mA  iB 2
R1
4K
If Q2 in active mode and β = 10
iC 2   iB 2  10(0.73mA)  7.3 mA and
iE 2  (   1) iB 2  11(0.73mA)  8.0 mA then
iR 2 
VBE3 0.7 V

 0.7 mA and
R2
1K
iB 3  iE 2  iR 2  8.0 mA  0.7 mA  7.3 mA
6
Transistor - Transistor Logic (TTL)
High Input, Low Output
*
VCC = 5 V

iRi
iR1
R1 =
1.6 K
VB1
VBE1
_
+
vi =
3.7V
_
+ + VBC1
_
For input high, i.e. vi = 3.7 V
 Assuming Q2 and Q3 are on and in
SATURATION.
iC2
iB2 + _
VBE2
VB1  3(0.8 V )  2.4 V and
R3 =
0.13 K
iRo=
1.0 mA
iB4
+
VBE4 _
VC2
off
sat
n


sat
Then, since Q2 is in saturation mode,
iC2 < β iB2 but VCE2 = 0.2 V and
Then, assuming Q4 is off, iB4 ≈ 0,
V  VC 2 5 V  1 V
iR1  CC

 2.5 mA
R1
1.6 K
and
iC 2  iR1  2.5 mA and
iE 2  iC 2  iB 2  2.5mA  0.65 mA  3.2 mA then
iR2
iR 2 
These verify that Q2 and Q3
are in saturation.
ECES 352 Winter 2007
VCC  VB1 5 V  2.4 V

 0.65 mA  iB 2
R1
4K
VC 2  VBE3  VCE 2  0.8 V  0.2 V  1.0 V
p
+
vo = 0.2V
_
iE2 iB3
+ _
VBE3
io
iRi 

R =4 K
+V
_ D
VBC1  VBE 2  VBE3  0.8 V
Then
iB 3  iE 2  iR 2  3.2 mA  0.8 mA  2.4 mA
2.5 mA
IC 2

 3.8    10
I B 2 0.65 mA
1 mA
IC3

 0.4    10
I B 3 2.4 mA
Ch 11 Bipolar Digital Pt. 3
VBE 3 0.8 V

 0.8 mA and
R2
1K
iC 3  io 

5V  (0.2V  0.7V )
 1.0 mA
4K
So Q2 and Q3 are in saturation, and
vo = VCE3,sat = 0.2 V.
7
Transistor - Transistor Logic (TTL)
High Input, Low Output
*
iRiiR=
0.65 mA
iR1
R1 =
1.6 K
iB4
VB1
+ + VBC1
VBE1
_
_
+
vi =
3.7V
_
VB4
For input high, i.e. vi = 3.7 V
 What about our assumption that
VCC = 5 V
Q4 was off?
 Since Q3 is in saturation,
vo = VCE3,sat = 0.2 V.
 But we know that at B of Q4,
VB 4  VCC  iR1R1
R3 =
0.13 K
iRo =
1 mA
weakly on
iC2
iB2 + _
VBE2
+
VBE4 _
sat
iR2
io
p
So

But we also can write
VB 4  vo  1.0 V  0.2 V  0.8 V
VB 4  vo  VBE 4  VD  0.8 V
n
+
_vo = 0.2 V
iE2 iB3
+ _
VBE3
ECES 352 Winter 2007
+V
_ D
 5 V  2.5mA(1.6 K )  1.0 V


sat

Ch 11 Bipolar Digital Pt. 3
or
VBE 4  VD  0.4 V
So, while Q4’s E junction is
forward biased, the bias is not
enough to cause much current flow.
Here is the reason for the diode.
Without the diode, Q4 would be on
since VBE4 = 0.8 V and Q4 would be
in saturation producing a large,
undesirable and unnecessary current
into Q3.
8
Transistor - Transistor Logic (TTL)
High Input, Low Output
*
VCC = 5 V
iRiiR=
0.65 mA
iR1
R1 =
1.6 K
iB4
VB1
+ + VBC1
iE1 VBE1
_
_
+
vi =
3.7V
_
VB4
R3 =
0.13 K
iRo =
1 mA
weakly on
iC2
iB2 + _
VBE2
+
VBE4 _
+V
_ D
sat
p
n
+
vo
_vo = 0.2 V
iE2 iB3
+ _
VBE3
io
sat
iR2
ECES 352 Winter 2007
Ch 11 Bipolar Digital Pt. 3
In summary for input high, i.e.
vi = 3.7 V
 E junction of Q1 is reverse
biased, so iE1 ≈ 0.
 Current iR (~1 mA) flows out
C of Q1 into base of Q2
forcing Q2 into the saturation
mode.
 Most of iE2 goes into base of
Q3 forcing Q3 into saturation
mode
 So vo = VCE3,sat = 0.2 V and the
output is low.
 Q4 is only weakly on and not
providing much current to Q3
for the output low (0.2 V) and
in the static (unchanging)
mode.
9
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
R3 =
0.13 K
iR
VBE1
_
VB1
+ +V iB2=0
BC1
_
+
v_i i ≈ i
E1
R
V+
BE2 _
iR2=0
vo
3.7 V
off
iB3=0
+ _
VBE3
=0
off
A B
0
0
I
0.5 V
ECES 352 Winter 2007
Region I (A to B)
 For input low,
 Current iR flows out E of Q1
 Q1 is in saturation since iE1 ≈ iR1 and iC1
≈ iB2 ≈ 0
 Q2 is in cutoff since iB2 ≈ 0
 Q3 is in cutoff since iB3 ≈ 0
 Output is high (3.7 V) since iC3 ≈ 0.
 Where is point B?
 Recall VB1 = 0.9 V for vi = 0.2 V, so VBC1, VBE2
and VBE3 are too small for current flow.
 Q2 must come on before Q3
 When does Q2 come on?
 We can write at the onset of Q2 coming on
 VB1 = vi + VBE1 ≈ vi + 0.7 V,
 But VB1 ≈ VBC1 + VBE2 since VBE3 ≈ 0.
 Assuming Q2 starts conducting when
VBC1 = VBE2 ≈ 0.6 V,
 Then vi + 0.7 V = 0.6 V + 0.6 V = 1.2V,
 So at point B, vi = 0.5 V
vi
Ch 11 Bipolar Digital Pt. 3
10
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
R1 =
1.6 K
iR1
iR
VB1
iC2
VBE4
V+
BE2 _
on
iE2 iB3 ≈ 0
VBE1 + +V
BC1
_
_
+
v_i
VB2
+ _
VBE3
iR2 ≈ 0
weakly on
Region II (B to C)
 For vi = 0.5 V ,
 Q2 is just turning on so iB2 , iC2 ≈ 0
 Q3 is still in cutoff
 Output is high, but starting to decrease.
 We can write for vo
vo  VCC  iR1R1  VBE 4  VD

Since Q4 and D are weakly on,
VBE4 = VD = 0.65 V so vo is given by
vo  5 V  0.65 V  0.65 V  R1 (iR1 )
off

 3.7V  1.6 K (iR1 )
We can approximate iR1 ≈ iC2 so
vo  3.7V  R1 (iC 2 ) and

vo
3.7 V
A
B
I

II
C


0
0
0.5 V
ECES 352 Winter 2007
vi
vo  1.6 K (iC 2 )
Since ΔVB2 ≈ Δvi , and VB2 = VBE2 + R2 iE2 , then
ΔVB2 = ΔVBE2 + R2 ΔiE2
Define Δic2 / ΔVBE2 = 1/re where
re = dynamic resistance of emitter junction
So ΔVB2 = ΔVBE2 + R2 ΔiE2 ≈ (re+R2) Δic2
So
 VB 2 
 vi 
   R1 
 so
vo   R1 (iC 2 )   R1 
 re  R2 
 re  R2 
vo
 R1
1.6 K
V


 1.45
vi re  R2
re  1K
V
Ch 11 Bipolar Digital Pt. 3
sin ce re  R2
11
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
R1 =
1.6 K
iR
iR1
VB1
VBE1 + +V iC2
BC1
_
_
+
v_i
V+
BE2 _
VB2
VBE4
on
iE2 iB3
iR2
+ _
VBE3
Region II (B to C)
 Where is point C?
 Q2 turned on at B, so Q2 in active
mode so VBE2 = 0.7 V
weakly on
 At C, Q3 is turning on, so VBE3 ≈ 0.7 V
 VB2 = VBE2 + VBE3 = 0.7 V + 0.7 V ≈ 1.4 V
 Since Q1 is in saturation, VCE1 ≈ 0.2 V so
vo dropping
vi = VB2 - VCE1 = 1.4V - 0.2V ≈ 1.2V
on
 What is the vo at this point C?
 Since for region II we found
vo
1.6 K

 1.45 then vo  1.45vi
vi
re  1K
 then from B to C
vo
3.7 V
A
2.7 V
vo  1.45vi  1.45(1.2V  0.5V )  1.0V
B
I
II
C
 and at point C
vo (C )  vo ( B)  vo ( B  C )
 3.7 V  1.0 V  2.7 V
0
0
0.5V 1.2V
ECES 352 Winter 2007
vi
Ch 11 Bipolar Digital Pt. 3
12
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
iR
R1 =
1.6 K
iR1
VB1
VBE1 + +V iC2
BC1
_
_
+
v_i
VBE4
on
sat V+ _
BE2
VB2
vo
3.7 V
A
B
I
2.7 V
0.2 V
0
0
iE2 iB3
+ _
iR2 VBE3
II
C III
D
0.5V 1.2V 1.4V
ECES 352 Winter 2007
Region III (C to D)
 Beyond point C,
 Q2 and Q3 are on
 As vi increases, more of iR (~ 1 mA) is
directed into base of Q2, so Q2 goes into
weakly on
active and then saturation.
 Q2 produces a large current iE2 (~3 mA),
and most of it goes into base of Q3 so
vo = dropping
Q3 goes into active and then saturation.
on
 At point D,
 Both Q2 and Q3 are entering saturation so
VB2 = VBE2+VBE3 = 0.8 V + 0.8 V = 1.6 V.
 Since Q1 is still in saturation,VCE1 ≈ 0.2 V
so vi = VB2 - VCE1 = 1.6V - 0.2V = 1.4V
 What is the vo at this point D?
 Since Q3 is entering saturation,
vo = VCE3,sat = 0.2 V.
 So from point C to D, the output drops sharply
from 2.7 V to 0.2 V as Q3 turns on and moves
rapidly from active into saturation as the input
increases from 1.2 V to 1.4 V.
vi
Ch 11 Bipolar Digital Pt. 3
13
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
iR
R1 =
1.6 K
VB1
VBE1 + +V
BC1
_
_
+
v_i
iR1
iC2
VBE4
sat
iE2 iB3
sat V+ _
BE2
VB2
vo
3.7 V
A
B
I
2.7 V
+ _
iR2 VBE3
sat
IV
E
II
C III
D
0.2 V
0.1 V
0
weakly on
0.5V 1.2V 1.4V
ECES 352 Winter 2007
3.7 V
Region IV (D to E)
 Beyond point D,
 Q2 and Q3 are on and are being
driven deeper into saturation
 As vi increases further, all of iR
(~1 mA) is directed into base of Q2,
so Q2 goes deeply into saturation.
 Q2 produces a large current iE2
(~3 mA), and most goes into base of
Q3 so Q3 goes deeply into saturation
also so vo gets even smaller,
i.e vo = VCE3,sat  0.1 V.
 So from point D to E, the output drops
very slowly from 0.2 V to 0.1 V as the
input increases from 1.4 V to 3.7 V.
 At point D, the E junction of Q1 is
forward biased and its C junction is
forward biased, so Q1 is still in the
forward saturation mode.
 At point E, the E junction of Q1 is reverse
biased and its C junction is forward biased,
so Q1 is in the inverse mode.
vi
Ch 11 Bipolar Digital Pt. 3
14
Voltage Transfer Characteristic for TTL
VCC = 5 V
*
Summary of transfer characteristic
R3 =
0.13 K
iR


+
v_i

Q1 in saturation, Q2 and Q3 off
vo
Q2 comes on
VOH =3.7 V
A B
2.7 V
I
II
C III
Q3 comes on,
Q2 heads towards saturation
D
VOL=
0.1 V
0
0.5V 1.2V 1.4V
VIL
VIH
ECES 352 Winter 2007
Q3 reaches saturation,
Q2 already in saturation
Q1 comes out of saturation
IV
E
3.7 V
vi
When the input is low,
 The current iR goes out the E of Q1
 So Q2 and Q3 get no base current and are off
 So the output is high
When the input increases,
 Some of iR gets directed into the B of Q2, so
Q2 gets some base current and comes on in
active mode
 C current of Q2 increases, so IR drop across R1
increases and output voltage drops (B to C)
 As Q2 comes on, it provides base current to
Q3 and Q3 come on in active mode (C).
When the input increases further,
 More of iR gets directed into the C of Q1, so
Q2 gets more base current and moves into the
saturation mode (C to D)
 Q2 provides more base current to Q3 and then
Q3 moves into saturation mode (D).

Further increases in the input direct all of iR into
the C of Q1, so Q2 gets even more base current and
moves deeper into the saturation mode (D to E).
Similarly, Q3 moves deeper into saturation.
Ch 11 Bipolar Digital Pt. 3
15
Voltage Transfer Characteristic for TTL
*
VCC = 5 V
Noise Margins

Noise Margin for low state NML = VIL -VOL
 VOL = low output voltage for typical high
input voltage = 0.1 V
 VIL= maximum input voltage recognized
as a low input = 0.5 V
 NML = VIL-VOL = 0.5 V - 0.1 V = 0.4 V

Noise Margin for high state NMH = VOH -VIH
 VOH = high output voltage for typical low
input voltage = 3.7 V
 VIH= minimum input voltage recognized
as a high input = 1.4 V
 NMH = VOH -VIH = 3.7 V - 1.4V = 2.3 V

Noise margins are very unequal for this
technology.
 Noise margins are similar to simplified
TTL and RTL cases.
 Noise margins cannot be easily changed.
iR
+
v_i
vo
vo
VOH =3.7 V
A B
I
2.7 V
NML
VOL=
0.1 V
0
II
C III
D
0.5V 1.2V 1.4V
VIL
VIH
ECES 352 Winter 2007
IV
NMH
E
3.7 V
vi
Ch 11 Bipolar Digital Pt. 3
16