Download Lecture 5: Dual-Threshold Low-Power Devices

ELEC 5270-001/6270-001 (Fall 2006)
Low-Power Design of Electronic Circuits
(Formerly ELEC 5970-003/6970-003)
Dual-Threshold Low-Power Devices
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University, Auburn, AL 36849
http://www.eng.auburn.edu/~vagrawal
[email protected]
Fall 06, Sep 14
ELEC5270-001/6270-001 Lecture 5
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Subthreshold Conduction
Ids
Vgs – Vth
-Vds
I0 exp( ───── ) × (1– exp ── )
nVT
VT
=
Ids
Subthreshold
region
1mA
100μA
10μA
1μA
100nA
10nA
1nA
100pA
10pA
Sunthreshold slope
Vth
0
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Saturation region
0.3
0.6
0.9
1.2
ELEC5270-001/6270-001 Lecture 5
1.5
1.8 V
Vgs
2
Thermal Voltage, vT
VT = kT/q = 26 mV, at room temperature.
When Vds is several times greater than VT
Ids
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=
Vgs – Vth
I0 exp( ───── )
nVT
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Leakage Current
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Leakage current equals Ids when Vgs= 0
Leakage current, Ids = I0 exp(-Vth/nVT)
At cutoff, Vgs = Vth , and Ids = I0
Lowering leakage to 10-bI0
Vth = bnVT ln 10 = 1.5b × 26 ln 10 = 90b mV
Example: To lower leakage to I0/1,000
Vth = 270 mV
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Threshold Voltage
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Vth = Vt0 + γ[(Φs+Vsb)½- Φs½]
Vt0 is threshold voltage when source is at
body potential (0.4 V for 180nm process)
Φs = 2VT ln(NA /ni ) is surface potential
γ = (2qεsi NA)½tox /εox is body effect
coefficient (0.4 to 1.0)
NA is doping level = 8×1017 cm-3
ni = 1.45×1010 cm-3
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Threshold Voltage, Vsb=1.1V
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Thermal voltage, VT = kT/q = 26 mV
Φs = 0.93 V
εox = 3.9×8.85×10-14 F/cm
εsi = 11.7×8.85×10-14 F/cm
tox = 40 Ao
γ = 0.6 V½
Vth = Vt0 + γ[(Φs+Vsb)½- Φs½] = 0.68 V
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A Sample Calculation
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VDD = 1.2V, 100nm CMOS process
Transistor width, W = 0.5μm
OFF device (Vgs = Vth) leakage
I = 20nA/μm, for low threshold transistor
 I0 = 3nA/μm, for high threshold transistor
 0
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100M transistor chip

Power = (100×106/2)(0.5×20×10-9A)(1.2V) = 600mW
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Power = (100×106/2)(0.5×3×10-9A)(1.2V) = 90mW
for all low-threshold transistors
for all high-threshold transistors
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Dual-Threshold Chip
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Low-threshold only for 20% transistors on
critical path.
Leakage power = 600×0.2 + 90×0.8
= 120 + 72
= 192 mW
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Dual-Threshold CMOS Circuit
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Dual-Threshold Design
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To maintain performance, all gates on the
critical path are assigned low Vth .
Most of the other gates are assigned high
Vth . But,
Some gates on non-critical paths may
also be assigned low Vth to prevent those
paths from becoming critical.
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Integer Linear Programming (ILP) to
Minimize Leakage Power
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Use dual-threshold CMOS process
First, assign all gates low Vth
Use an ILP model to find the delay (Tc) of the
critical path
Use another ILP model to find the optimal Vth
assignment as well as the reduced leakage
power for all gates without increasing Tc
Further reduction of leakage power possible by
letting Tc increase
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ILP -Variables
For each gate i define two variables.
 Ti : the longest time at which the output
of gate i can produce an event after the
occurrence of an input event at a primary
input of the circuit.
 Xi : a variable specifying low or high Vth
for gate i ; Xi is an integer [0, 1],
1  gate i is assigned low Vth ,
0  gate i is assigned high Vth .
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ILP - objective function
Leakage power:
Pleak  Vdd  I leaki
i
minimize the sum of all gate leakage currents, given by
Min   X i  I Li  1  X i   I Hi 
i
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ILi is the leakage current of gate i with low Vth
IHi is the leakage current of gate i with high Vth
Using SPICE simulation results, construct a leakage
current look up table, which is indexed by the gate
type and the input vector.
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ILP - Constraints

For each gate
(1)
Ti  T j  X i  DLi  1  X i   DHi
Gate i
Ti
output of gate j is fanin of gate i
Gate j
(2)

0  Xi 1
Tj
Max delay constraints for primary outputs (PO)
Ti  Tmax
(3)
Tmax is the maximum delay of the critical path
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ILP Constraint Example
0
1
2
3
Ti  T j  X i  DLi  1  X i   DHi
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Assume all primary input (PI) signals on the left arrive at the
same time.
For gate 2, constraints are
T2  T0  X 2  DL 2  1  X 2   DH 2
T2  0  X 2  DL2  1  X 2   DH 2
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ILP – Constraints (cont.)
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DHi is the delay of gate i with high Vth
DLi is the delay of gate i with low Vth
A second look-up table is constructed and
specifies the delay for given gate type and
fanout number.
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ILP – Finding Critical Delay
Ti  Tmax
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Tmax can be specified or be the delay of longest path (Tc).
To find Tc , we change constraints (2) to an equation,
assigning all gates low Vth
0  Xi 1
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Xi 1
Maximum Ti in the ILP solution is Tc.
If we replace Tmax with Tc , the objective function minimizes
leakage power without sacrificing performance.
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Power-Delay Tradeoff
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If we gradually increase Tmax from Tc , leakage
power is further reduced, because more gates
can be assigned high Vth .
But, the reduction trends to become slower.
When Tmax = (130%) Tc , the reduction about
levels off because almost all gates are assigned
high Vth .
Maximum leakage reduction can be 98%.
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Power-Delay Tradeoff
1
0.9
Normalized Leakage Power
0.8
C432
0.7
C880
0.6
C1908
0.5
0.4
0.3
0.2
0.1
1
1.1
1.2
1.3
1.4
1.5
Normalized Critical Path Delay
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Leakage Reduction
Un
Optimized Leakage
Sun
Optimized
Leakage
Sun
Number Tc
Circuit
optimized Ileak (μA) Reduction OS 5.7
Ileak (μA)
Reduction OS 5.7
of gates (ns)
Ileak (μA) (Tmax=Tc)
%
CPU s (Tmax=1.25Tc)
%
CPU s
C432
160
0.75
2.620
1.022
61.0
0.25
0.132
95.0
0.25
C499
182
0.39
4.293
3.464
19.3
0.31
0.225
94.8
0.30
C880
328
0.67
4.406
0.524
88.1
0.54
0.153
96.5
0.53
C1355
214
0.40
4.388
3.290
25.0
0.33
0.294
93.3
0.36
C1908
319
0.57
6.023
2.023
66.4
0.57
0.204
96.6
0.56
C2670
362
1.26
5.925
0.659
90.4
0.68
0.125
97.9
0.53
C3540
1097
1.75
15.622
0.972
93.8
1.71
0.319
98.0
1.70
C5315
1165
1.59
19.332
2.505
87.1
1.82
0.395
98.0
1.83
C6288
1177
2.18
23.142
6.075
73.8
2.07
0.678
97.1
2.00
C7552
1046
1.92
22.043
0.872
96.0
1.59
0.445
98.0
1.68
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Dynamic & Leakage Power
Comparison
I sub  u0Cox
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Weff
Leff
 Vgs  Vt  
 V 
2
  1  exp  ds  
vth e1.8 exp 


 nvth  
 Vt  
VT (thermal voltage, kT/q) and Vth (threshold voltage)
both depend on the temperature; leakage current also
strongly depends on temperature.
Spice simulation shows that for a 2-input NAND gate
- with low Vth , Isub @ 90ºC = 10 × Isub @ 27ºC
- with high Vth , Isub @ 90ºC = 20 × Isub @ 27ºC
To manifest the projected contribution of leakage to the
total power, we compare dynamic and leakage power @
90ºC.
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Dynamic & Leakage Power
Comparison (cont.)
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Without considering glitches, the dynamic
power is estimated by an event driven
simulator, and is given by
0.5  Cinv  Vdd   Ti FOi
2
Pdyn 

Edyn
T

i
10001.2 T c 
We apply 1000 random test vectors at PIs
with a vector period of 120% Tc , and
calculate the total number of weighted (by
node capacitance) transitions in the circuit.
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Dynamic & Leakage Power @90oC
Circuit
Pdyn
(μW)
Pleak1
(μW)
Pleak1/
Pdyn %
Pleak2
(μW)
Pleak2/
Pdyn %
C432
71.17
26.20
36.8
10.22
14.3
C499
149.81
42.93
28.7
34.64
23.1
C880
135.19
44.06
32.6
5.24
3.8
C1355
162.39
43.88
27.0
32.90
20.3
C1908
185.60
60.23
33.4
20.23
10.9
C2670
92.64
59.25
64.0
6.59
7.1
C3540
218.41
156.22
71.5
9.72
4.4
C5315
299.61
193.32
64.6
25.05
8.4
C6288
215.12
231.42
108.0
60.75
28.2
C7552
229.13
220.43
96.2
8.72
3.8
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Power in μW
Dynamic & Leakage Power @90oC
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Summary
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Leakage power is a significant fraction of the
total power in nanometer CMOS devices.
Leakage power increases with temperature; can
be as much as dynamic power.
Dual threshold design can reduce leakage.
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Reference: Y. Lu and V. D. Agrawal, “Leakage and
Dynamic Glitch Power Minimization Using Integer
Linear Programming for Vth Assignment and Path
Balancing,” Proc. PATMOS, 2005, pp. 217-226, access
paper at
http://www.eng.auburn.edu/~vagrawal/TALKS/PATMOS-134.pdf
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