Download ppt - UCSD VLSI CAD Laboratory

Constructing Current-Based Gate Models
Based on Existing Timing Library
Andrew Kahng, Bao Liu, Xu Xu
UC San Diego
http://vlsicad.ucsd.edu
Outline
 Gate Modeling Background
 Problem Formulation
 Approximation and Regression
 Applications
 Experiments
 Conclusion
Gate Models
 K-factor lookup tables
1.
Dg = f(Cload, Tr)
2.
Trout = g(Cload, Tr)
 Efficient capacitance Ceff for
distributed load capacitance

To achieve identical gate delay
(and output signal transition time
at the same time!)

E.g., by achieving the same
average gate output current
Calculating Effective Capacitance
Ceff = Cload
Trout = g(Ceff, Tr)
Ceff s.t.
Iout(Ceff)=Iout(load)
1. If (Ceff > Cload || Ceff < 0)
2.
Return Cload
3. Else if(DCeff < e)
4.
May not converge

No equivalent gate delay and
Trout at the same time

Waveforms are not ramp
functions!
Return Ceff
5. Else
6.

Continue iteration
Current-Based Transistor Model
 MOSFET is a voltage-controlled current source,
e.g., as in the alpha-power-law model


0

 W Pc
Ids  
(Vgs  Vt )  / 2
 Leff Pv
 W Pc(Vgs  Vt ) 
 Leff
Vgs  Vt
Vds  Pv(Vgs  Vt ) 
Vds  Pv(Vgs  Vt ) 
 For a simple inverter, gate output current is given
by one of the transistors
 An equivalent inverter macro-model for an inverting
complex gate
  current-based gate modeling
Current-Based Gate Modeling
 Consists of a lookup table I(Vi, Vo) and C(Vi, Vo)
Vi
Vo
R
Vi
I(Vi, Vo)
C
Voltage-Based
Current-Based
 Transient analysis for output signal waveform
Gate Pre-Characterization
 Current-based gate models need additional precharacterization, e.g., I(Vi, Vo), given by SPICE DC
sweep analysis
 Cadence Effective Current Source Model (ECSM)
Rise_transition (template) {
index_1: // slew rate
index_2: // load cap
values: // output Tr
ecsm_waveform (name1) {
index_3: // output voltage
values: // time point
}
}
 Synopsys Composite Current Source Model (CCS)
Outline
 Gate Modeling Background
 Problem Formulation
 Approximation and Regression
 Applications
 Experiments
 Conclusion
Constructing Current-Based Gate
Model From Existing Timing Libraries
 Given gate delays and output slew rates for load
caps and input slew rates, find an equivalent
current-based gate model, e.g., I(Vi, Vo) and C
1.
Dg = f(Cload, Tr)
2.
Trout = g(Cload, Tr)
I(Vi, Vo)
Tr
C
Cload
Dg
Vi
Cload
Trout
Tr
I
Vi
Vo
C
Inverse Problem
 To find an unknown underlying physical process by
a set of measurements
 Q=CV
 Inhomogeneous Fredholm integral equations of the
first kind
Dg  0.5Tr in
 I (Vi,Vo)dt  0.5(C  C
L
)Vdd
0
Dg  0.5Tr in 0.5Tr  out
 I (Vi,Vo)dt  (0.8  0.2)(C  C
Dg  0.5Tr in 0.5Tr  out
L
)Vdd
Solving an Inverse Problem
 Integral equations  differential equations
 Apply interpolation to reduce variables to those in
the I(Vi, Vo) lookup table
a I
i i
 0.5(C  C L )Vdd
i
b I
i i
 (0.8  0.2)(C  C L )Vdd
i
 Inverse problem solutions are extremely sensitive to
input data perturbations!
 Inverse problem  Optimization w/ objective A +  S
(A: accuracy, S: smoothness, : weighting factor)
Outline
 Gate Modeling Background
 Problem Formulation
 Solution: Approximation and Regression
 Applications
 Experiments
 Conclusion
Polynomial Regression of I(Vi,Vo)
 A priori knowledge:
 Approximate I(Vi, Vo) by a quadratic polynomial
 9+1 coefficients in a limited range
Polynomial Regression of I(Vi,Vo)
I (Vi ,Vo )  a 00  a 01Vo  a 02Vo
 a10Vi  a11ViVo  a12ViVo
2
 a 20Vi  a 21Vi Vo  a 22Vi Vo
2
I (0,0)
I (0,1)
I (1,0)
I (11
,)

Vi I (Vi ,Vo )

Vo I (Vi ,Vo )






0
0
0
0
0
0
2
2
2
2
a 00 , a 20
a 01 , a 02 , a10
a 00  a 01  a 02
a 00  a10  a 20
a 01  a11  a 21
a10  a11  a12






0
0
0
0
0
0
Our Constructive Method
1. Start with an initial polynomial coefficient
2. For each iteration
3.
Perturb a coefficient ai’ = ai + d
4.
Compute mean square gate delay mismatch e
5.
If e reduces, commit perturbation ai = ai + d
6.
Else, go other direction ai = ai – d
7.
Stop if no improvement
8.
Reduce step d for another iteration
9. Compute I(Vi, Vo) and C
Applications
 More accuracy, arbitrary waveform
 Efficiency advantage over SPICE simulation
 Gate delay calculation for
 Long
interconnects
 Cross-coupling
 Supply
interconnects
voltage drop effect
 Supply current calculation
 Noise calculation
Supply Voltage Variation Effect on
Gate Delay Calculation
I '  I (Vi ' ,Vo ' )
Vi '  Vi  DV
Vo '  Vo  DV
 There exists an equivalent inverter macro-model
for each input combination for any (inverting)
complex gate
 Adjust input and output voltages for I(Vi, Vo) table
lookup for a falling input signal, but not for a rising
input signal
Experiments
 BPTM 70nm technology cell library
 Compare (our) constructed and (SPICE simulation
based) pre-characterization models
Our
Constructed
Quad. Pre Characterization
Cubic Pre Characterization
m
s
m
s
m
s
invx4
1.25
5.7
9.73
45.2
11.12
37.8
invx8
1.85
16.9
12.93
27.2
14.67
27.8
4.8
7.06
152.7
5.91
56.5
nor2x4 0.46
Experiments
 Gate delays by (1) our model and (2) pre-characterized
model normalized by SPICE simulation results
For Ideal (1.0V) Supply Voltage
97.4 99.0
101.0 97.8
94.9
(1)
93.0
(2)
100.0 98.7
(1)
98.4
(2)
104.3 101.8 100.0
(1)
For Degraded (0.9V) Supply Voltage
102.0 105.4 106.7 108.6 101.2 106.8 108.6 106.9
(2)
102.1 99.8
(1)
107.8 106.4 106.6
106.2 107.8 106.4 106.6 108.3
(2)
100.0 99.6
97.8
99.3
102.6 99.0
98.7
99.1
95.7
98.0
100.0 102.5 101.2 100.6 100.0
95.5
103.9 100.8 100.2 99.5
100.0 97.6
98.8
98.5
100.8 99.6
95.6
97.9
99.2
98.7
98.7
100.1
97.9
100.2
Summary
 Utilize existing timing libraries for application of
novel current-based gate modeling
 Wide range of applications: supply current
calculation, delay calculation for complex
waveforms, e.g., resistive shielding, crosstalk
coupling, supply voltage variation, etc.
 Slightly less accurate than pre-characterized
current-based gate models, e.g., within 8.6% vs.
4.4% for gate delay calculation with varied supply
voltage
 Reasonable runtime for model construction, 28.3
seconds in average on a 2.8GHz P4 system
Thank you !