Download Intel-CERN-14-April-2008

FROM SINGLE- TO MANY-CORE COMPUTING
14 April 2008
Dr Herbert Cornelius
Intel EMEA
Copyright © 2008 Intel Corporation. All rights reserved.
Risk Factors

This presentation contains forward-looking statements that involve a number of risks and uncertainties. These statements do not reflect the potential impact of any
mergers, acquisitions, divestitures, investments or other similar transactions that may be completed in the future, with the exception of the Numonyx transaction.
Our forward-looking statements for 2008 reflect the expectation that the Numonyx transaction will close during the first quarter. The information presented is
accurate only as of today’s date and will not be updated. In addition to any factors discussed in the presentation, the important factors that could cause actual
results to differ materially include the following: Factors that could cause demand to be different from Intel's expectations include changes in business and economic
conditions, including conditions in the credit market that could affect consumer confidence; customer acceptance of Intel’s and competitors’ products; changes in
customer order patterns, including order cancellations; and changes in the level of inventory at customers. Intel’s results could be affected by the timing of closing of
acquisitions and divestitures. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to
reduce in the short term and product demand that is highly variable and difficult to forecast. Additionally, Intel is in the process of transitioning to its next generation
of products on 45 nm process technology, and there could be execution issues associated with these changes, including product defects and errata along with lower
than anticipated manufacturing yields. Revenue and the gross margin percentage are affected by the timing of new Intel product introductions and the demand for
and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing
pressures and Intel’s response to such actions; Intel’s ability to respond quickly to technological developments and to incorporate new features into its products; and
the availability of sufficient components from suppliers to meet demand. The gross margin percentage could vary significantly from expectations based on changes
in revenue levels; product mix and pricing; capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for
sale; excess or obsolete inventory; manufacturing yields; changes in unit costs; impairments of long-lived assets, including manufacturing, assembly/test and
intangible assets; and the timing and execution of the manufacturing ramp and associated costs, including start-up costs. Expenses, particularly certain marketing
and compensation expenses, vary depending on the level of demand for Intel's products, the level of revenue and profits, and impairments of long-lived assets. Intel
is in the midst of a structure and efficiency program that is resulting in several actions that could have an impact on expected expense levels and gross margin. We
expect to complete the divestiture of our NOR flash memory assets to Numonyx. A delay or failure of the transaction to close, or a change in the financial
performance of the contributed businesses could have a negative impact on our financial statements. Intel’s equity proportion of the new company’s results will be
reflected on its financial statements below operating income and with a one quarter lag. The tax rate expectation is based on current tax law and current expected
income. The tax rate may be affected by the jurisdictions in which profits are determined to be earned and taxed; changes in the estimates of credits, benefits and
deductions; the resolution of issues arising from tax audits with various tax authorities , including payment of interest and penalties; and the ability to realize deferred
tax assets. Gains or losses from equity securities and interest and other could vary from expectations depending on fixed income and equity market volatility; gains
or losses realized on the sale or exchange of securities; gains or losses from equity method investments; impairment charges related to marketable, non-marketable
and other investments; interest rates; cash balances; and changes in fair value of derivative instruments. Intel’s results could be affected by the amount, type, and
valuation of share-based awards granted as well as the amount of awards cancelled due to employee turnover and the timing of award exercises by employees.
Intel's results could be impacted by adverse economic, social, political and physical/infrastructure conditions in the countries in which Intel, its customers or its
suppliers operate, including security concerns, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel's
results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory
matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC
reports. A detailed discussion of these and other risk factors that could affect Intel’s results is included in Intel’s SEC filings, including the report on Form 10-K for
the fiscal year ended December 29, 2007.
Copyright © 2008 Intel Corporation. All rights reserved.
Computing …
Copyright © 2008 Intel Corporation. All rights reserved.
*Other names and brands may be claimed as the property of others.
NEED FOR SPEED & DENSITY
Tera-Scale Computing
TERAOPS Performance
TERABYTES Memory Bandwidth
TERABITS I/O Throughput
Copyright © 2008 Intel Corporation. All rights reserved.
NEED FOR SPEED & DENSITY
Tera-Scale Computing
TERAOPS Performance
TERABYTES Memory Bandwidth
TERABITS I/O Throughput
Copyright © 2008 Intel Corporation. All rights reserved.
Some Observations Regarding Benefits vs. Efforts
 The number of transistors on a chip doubles every 24 month
 Processor architectures changed from area limited to power limited




ILP useful for ~4 parallel instructions
Instruction pipeline useful if  30 stages
Power consumption grows about cubically with frequency
Processing capability grows faster than memory speed
 Single core performance is growing slower than it used to be
 SMT/HT can mitigate the situation for certain workloads
 CMP/Multi-Core seems to be a reasonable “compromise”
 Opportunity for performance to increase faster than Moore’s Law
Copyright © 2008 Intel Corporation. All rights reserved.
1 TFLOPS on a Chip
62W
Experimental Research Test Chip
100M Transistors – 80 Tiles – 275mm2
Copyright © 2008 Intel Corporation. All rights reserved.
Industry Trend to Multi/Many-Core
Intel Tera-Scale Computing Research Program:
www.intel.com/go/terascale
Many-Core
Multi-Core
Dual-Core
Hyper-Threading
QUAD-CORE
Multi Processor
Energy Efficient Petascale with Multi-threaded Cores
Copyright © 2008 Intel Corporation. All rights reserved.
All products, dates, and figures are preliminary and are subject to change without any notice.
On-Time 2 Year Cycles
Moore´s Law is (still) leading the Chip Industry
Copyright © 2008 Intel Corporation. All rights reserved.
Future options subject to change; Source: Intel
Going Forward
New Materials and Designs
Intel
Architecture
Core
Core Enhancements
Multi to Many-Core
Platform Enhancements
Copyright © 2008 Intel Corporation. All rights reserved.
Going Forward
Tri-Gate, Nanotubes 
Intel
Architecture
Core
MMX  SSE  AVX 
Dual  Quad  Octo 
PCIe, IMC, QPI, SOC 
Copyright © 2008 Intel Corporation. All rights reserved.
Memory and CPU package architectures for
addressing bandwidth challenges
Package Technology to Address the Memory Bandwidth Challenge for Tera-scale Computing, Intel Technology Journal, Volume 11, Issue 3, 2007
Copyright © 2008 Intel Corporation. All rights reserved.
Future Vision, does not represent real Intel product
Copyright © 2008 Intel Corporation. All rights reserved.
The Magic of 45 nm
PERFORMANCE
(Spectrum of Intel Architecture)
SYSTEM
ON A CHIP
Notebook, Desktop and Server
Ultra-low Cost and
Power Optimized
Architecture
Intel® Core™ 2 and Nehalem
Architecture
Visual Computing
and HPC Optimized
Architecture
POWER
Source: Intel Internal
Copyright © 2008 Intel Corporation. All rights reserved.
All plans, products, dates, and figures are preliminary and are subject to change without any notice.
Bringing IA Programmability and Parallelism
to High Performance & Throughput Computing
IA++
IA++
IA++
IA++
IA++
IA++
IA++
IA++
…
Special
Function
& I/O
…
Cache
Copyright © 2008 Intel Corporation. All rights reserved.
…
…
…
…
IA++
…
IA++
IA++
IA++
 Highly parallel, IA programmable
architecture in development
 Ease of scaling for software ecosystem
 Array of enhanced IA cores
 New Cache Architecture
 New Vector Processing Unit
 Scalable to TFLOPS performance
Future options subject to change without notice.
Tick/Tock: Our Model for Sustained
Microprocessor Leadership
Intel®
Core™
Sandy
Bridge
Penryn
Nehalem
Westmere
NEW
Microarchitecture
Compaction/
Derivative
NEW
Microarchitecture
Compaction/
Derivative
NEW
Microarchitecture
2006
2007
2008
2009
2010
65nm
45nm
45nm
32nm
Forecast
e.g. Intel® QuickPath Architecture
Copyright © 2008 Intel Corporation. All rights reserved.
Future options subject to change without notice.
32nm
Parallel Programming Considerations
 Finding or Introducing Parallelism
 Serial vs. Parallel Algorithm
 Partitioning
– Data-Parallelism
– Functional-Parallelism
– Manager/Worker Approach
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




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Copyright © 2008 Intel Corporation. All rights reserved.
Implementing Parallelism
Correctness
Speed-Up
Scalability
Overhead
Communication/Synchronization
Load-Imbalance
Granularity
Platform Related
Intel’s Software Tools and Support
Intel® Threading Tools
Cluster Tools
ISN & ISC
ISS
Performance | Compatibility | Support | Productivity | Cross-Platform
www.intel.com/software
Copyright © 2008 Intel Corporation. All rights reserved.
INTEL® ARCHITECTURE
Continuous Innovation and sustained Leadership
Moving ahead to Multi/Many-Core Processors
45nm Production since 2007
2nd Generation Quad-Core – 100 GFLOPS/Processor today
Advanced Next Generation Nehalem Architecture in 2008
High Density Platforms
Energy Efficient
Leading (Parallel) Software Tools
Performance Easy to Use
Copyright © 2008 Intel Corporation. All rights reserved.
Industry’s First 45nm High-K
Quad
Core
100 GFLOPS/PROCESSOR
Dual
Core
Server
Desktop
*Codenames
Copyright © 2008 Intel Corporation. All rights reserved.
Mobile
What about Amdahl’s Law
S
max
p
( n) 
S = (max.) speed-up
n = number of processors/cores/threads
p = parallel portion of the application
1
1 p  np
p|n
18.00
16.00
14.00
12.00
10.00
8.00
6.00
4.00
2.00
0.00
1
2
4
8
% parallel
Gene Amdahl, "Validity of the Single Processor Approach to
Achieving Large-Scale Computing Capabilities", AFIPS
Conference Proceedings, (30), pp. 483-485, 1967.
Copyright © 2008 Intel Corporation. All rights reserved.
1.
00
0.
90
0.
80
0.
70
0.
60
0.
50
0.
40
0.
30
0.
20
16
0.
10
0.
00
Max. Speedup
Amdahl's Law for Parallelism
1
2
4
8
16
0.00
1.00
1.00
1.00
1.00
1.00
0.05
1.00
1.03
1.04
1.05
1.05
0.10
1.00
1.05
1.08
1.10
1.10
0.15
1.00
1.08
1.13
1.15
1.16
0.20
1.00
1.11
1.18
1.21
1.23
0.25
1.00
1.14
1.23
1.28
1.31
0.30
1.00
1.18
1.29
1.36
1.39
0.35
1.00
1.21
1.36
1.44
1.49
0.40
1.00
1.25
1.43
1.54
1.60
0.45
1.00
1.29
1.51
1.65
1.73
0.50
1.00
1.33
1.60
1.78
1.88
0.55
1.00
1.38
1.70
1.93
2.06
0.60
1.00
1.43
1.82
2.11
2.29
0.65
1.00
1.48
1.95
2.32
2.56
0.70
1.00
1.54
2.11
2.58
2.91
0.75
1.00
1.60
2.29
2.91
3.37
0.80
1.00
1.67
2.50
3.33
4.00
0.85
1.00
1.74
2.76
3.90
4.92
0.90
1.00
1.82
3.08
4.71
6.40
0.95
1.00
1.90
3.48
5.93
9.14
1.00
1.00
2.00
4.00
8.00
16.00