Download Sleep Transistor Circuits for Fine-Grained Power Switch

Sleep Transistor Circuits for
Fine-Grained Power Switch-Off
with Short Power-Down Times
Mohammad Hashem Haghbayan
Technical Faculty of Tehran University
VLSI Seminar Dr.Fakhraie
St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2,
J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2, D. Schmitt-Landsiedel1
1
2
3
Technical University Munich, Munich, Germany
Infineon Technologies, Munich, Germany
now with IBM, Böblingen, Germany
Outline
 Concept of fine-grained sleep transistor scheme
 16 bit Multiply-Accumulate-Unit as demonstrator
 Measurement methodology & techniques for
minimum power-down time reduction
 Fractional switch activation for slow operation mode
 Double switch scheme for fast block activation
 Conclusion
2
Footer and Header fine-grain sleep transistor
implementation in NAND gate [1]
3
Coarse-Grain Sleep Transistors[1]
4
Grid style sleep transistor implementations[1]
5
Ring style sleep transistor implementations[1]
6
Concept of Fine-Grained Power Switch-Off
 SOC with large blocks
SOC
- individual activity profile
DSP
- varying frequency
requirements
 Block level MTCMOS
technology scaling
increases leakage
Application
Processor
 Fine-grained MTCMOS
- small sub-blocks
- short power-down times
7
16 bit MAC System Overview
 16 bit MAC as representative SOC building block
 Two stage pipeline
- booth(2) precoding stage
- Han Carlson adder stage
 High threshold PMOS sleep transistor (3 x 128 x 1.5m)
 Input / output cache and BIST for full speed testing
 Standard-cell based design using multi-Vth option
 130nm low-power CMOS technology
8
Multiply-Accumulate-Unit[2]
9
maximum frequency [MHz]
Measurement of Max. Frequency[2]
1000
800
no switch
large switch
small switch
600
400
1
1.2
1.4
supply voltage [V]
1.6
5 % speed degradation and 8.5 % area overhead
9.5 % speed degradation and 2.8 % area overhead 10
Leakage Reduction[2]
leakage current [A]
10
10
10
10
10
-4
active switch
inactive switch
SC: VGS=1.8V-VDD
-5
SC: VGS=300mV
-6
Super cut-off (SC):
dramatically reduced
leakage for appropriate
underdrive values
achievable
-7
-8
GIDL
10
10
-9
85 °C
-10
0.5
1
supply voltage VDD [V]
1.5
11
Frequency vs. Leakage Features[2]
max frequency leakage reduction (1.2V)
no switch
1GHz @1.6V
1x
large switch
950MHz
192x
86x
– with boosting
970 MHz
192x
86x
– super cut-off 0.3V
950 MHz
1179x
5508x
– SC: VGS=1.8V–VDD
950MHz
675x
2628x
small switch
905 MHz
ILEAK (large switch) / 3
25 °C
85 °C
12
virtual rail potential [V]
Leakage Reduction & Overhead[2]
1.2
1
0.8
0.6
what is the minimum
power-down time?
0.4
0.2
0
0
10
20
30
time after cut-off [s]
40
13
supply current A]
[
Minimum Power-Down Time[2]
4
leakage for system always in active mode
minimum sleep time
5.8 s
3
2
leakage without switching overhead
1
0
0
leakage for system always in sleep mode
20
40
60
80
100
block activation frequency fa [kHz]
Proposed measurement setup for experimental
determination of minimum power-down time
14
Temperature & Supply Voltage
Dependence[2]
supply current (norm.)
1.1
crossover
VDD=1.2V, T=25C
1
VDD=1.2V, T=85C
0.9
VDD=1.8V, T=25C
VDD=1.8V, T=85C
0.8
leakage currents 
0.7
( e.g. temperature, VDD, Vth )
0.6
 minimum power-down time 
0.5
0.4
0
 convergence time 
ideal value
0.5
1
1.5
power-down time (norm.)
2
15
Switching Overhead[2]
turn off
turn on
16
Charge Recycling Scheme[2]
turn off
turn on
17
Efficiency of Charge Recycling[2]
saved energy [pJ]
4
with charge recycling
without charge recycling
2
TCR
0
TnoCR
-2
25%
2
3
4
5
6
power-down time [s]
7
18
Impact of Virtual Supply
Reduction[2]
dynamic power [mW]
 Further reduction of minimum power-down time by
fractional switch activation in slow mode of operation
 Also observed: reduction of dynamic power
16
small switch
14 large switch
17.6%
12
10
6.8%
8
6
1.2V, 25 °C
4
200
400
600
frequency [MHz]
800
19
Power Impact of Adaptive Supply[2]
 Quadratic impact on dynamic
power consumption:
 Reasonable overhead only for
large logic blocks
slow
medium
fast
VDD
t
20
Virtual Supply Reduction[2]
 Reduced switching power
 min. power-down time 
 Linear impact on dynamic
power consumption:
slow
medium
fast
VDD
t
 Lower power saving but
negligible overhead
21
Power-Up Process
 Current spikes during block activation can cause
timing violations in surrounding blocks
 Two contributors:
- Recharging of internal circuit nodes
- Uncontrolled transient glitching activity
 Double switch scheme suppresses glitching
- Activate gates in two phases
- Demonstrated for filter circuit with NMOS sleep
transistors in 90nm low-power CMOS
22
Double Switch Scheme[2]
23
iactivate [mA]
iactivate [mA]
Impact of Double Switch Scheme[2]
8
no double switch
4
0
38.8 %
double switch
4
0
0
10
20
time [ns]
30
40
Measured results for filter circuit with NMOS sleep transistors
24
Conclusion[2]
 130nm CMOS 16-bit mixed Vth pipelined MAC
 PMOS sleep transistor results in up to 5500 x
leakage reduction with only 8.5% area overhead
and 5% frequency reduction
 Accurate measurement methodology for minimum
power-down time characterization
 Charge recycling & fractional switch activation for
reduction of minimum power-down time
 Double switch scheme for reduction of current
spikes during block activation
25
26
References
1- Sleep transistor design and implementation –
simple concept yet challenges to be optimum
Kaijian Shi, David Howard
2- sleep transistor circuits for fine-grained power
switch-off with short power down times
St. Henzler1, Th. Nirschl1,2, S. Skiathitis1,3, J. Berthold2,
J. Fischer1, Ph. Teichmann1, F. Bauer1, G. Georgakos2,
D. Schmitt-Landsiedel1
27