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A Monolithic Pixel Detector
in High-Voltage Technology
Ivan Perić
University of Mannheim
This work draws on the results from an ongoing research project
commissioned by the Landesstiftung Baden-Württemberg
Overview
 Introduction to the high-voltage CMOS process
 The idea behind the HV monolithic pixel Pixel electronics
 Electrical tests
- Noise
- Threshold dispersion
- Time over threshold
 Measurements with radioactive sources
- Estimation of the average MIP signal
- Images
 Outlook
VERTEX 2006
High-Voltage Technology
Two commonly used devices
G
S
D
n+
n+
n-
Channel
Asymmetrical
high-voltage NMOS
Low-doped N-well
Large depleted zone
p-
High voltages up to 50 – 70V
P-well implanted inside the N-well
G
B
S
n+
D
Channel
n+
pn-
Vertical HV NMOS
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Deep N-well
p-
Floating CMOS (Cross-Section)
Properties
of the chosen technology
Shallow N-well
P-well
P-well
Deep N-well
P Substrate
VERTEX 2006
50 V
9 m
- Maximal nominal
reverse bias of
deep N-well/P-substrate
diode:
50 V
- Depleted area of the diode:
maximal ~ 9m
- expected average MIP signal
in the depleted zone:
703 e
- Minimum gate size:
0.35 m
Monolithic Pixel Detector in HV Technology
4 pixels
Negatively biased P-substrate
Pixel-electronics inside the cathode (N-well)
Sensor cathode (N-well)
VERTEX 2006
Test Chip
The first test-chip have been implemented in a 0.35 m HV CMOS Process
Motivations
- to investigate the properties of deep N-well/P-substrate diode as a particle sensor
- to demonstrate that it is possible to implement complex CMOS pixel electronic in the diode cathode
(The electronics can involve
- signal amplification,
- continuous bias/reset,
- threshold discrimination,
- hit bit storage
- time stamp electronic)
VERTEX 2006
Pixel Electronic as implemented in the Test Chip
3.3 V
CR-RC
Comparator Latch
Bus driver
CSA
Readout bus
Tune DAC
AC coupling
-50 V
HV
N-well
P-substrate
The challenge: N-well is the sensor cathode and the carrier for the PMOS transistors at the same time
- Biasing of the N-well
- Signal cross-talk
- Prevention of the latch-up
VERTEX 2006
Amplifier
Capacitive feedback:
0.9 fF (drain diffusion) + 1.3 fF (metal-metal parasitic)
N-well
c
N-well
420 fF
In
a
Load bias
d
10/0.6 d
Out
Cascode bias
P-Substrate
Bias
9A
High gain CSA
The cross-talk:
every P-diffusion (a, b, c, d) is capacitively coupled to the sensor
Non-standard design
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Continuous Reset
Bias circuit
Bias
30 pA
Continuous feedback
with limited current*
In
*
Out
Feedback Current

Output Volt.
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Discharge with constant current
ToT
CR-RC Shaper
From now on, only NMOST…
30 pA
Base line bias
0.86 nA
Base line
Base line bias
22.1 fF (poly)
Amplifier out
0.6 nA
Base line
Foll. bias
7.6 fF (par.)
Disable
CR-RC
Threshold bias
Threshold
Pulse length is the linear measure
of the input signal amplitude
Tune DAC
Tune
VERTEX 2006
Simulation
Response to the signal of 1660 e
0,18
0,16
Amplifier output
Shaper output
Amplifier Output*
0,14
0,12
Signal/V
0,10
Simulated amplifier output without parasitic capacitances
0,08
0,06
Simulated amplifier output with parasitic capacitances
0,04
0,02
0,00
-0,02
0
1
2
3
Time/s
VERTEX 2006
4
5
Comparator and Latch
Differential current logic with NMOS diode as load to avoid digital cross-talk
Comparator/Buffer
Latch
OutP
OutN
InN
InP
Bias
OutN
OutP
SetN
6A
SetP
ResN
Bias
VERTEX 2006
ResP
Pixel Top-View
Bias (PMOS)
Amplifier and FB (PMOS)
Injection Capacitor
FB (NMOS)
Input Capacitor
Amplifier (NMOS)
Feedback
CR-RC Shaper
Select
P-Well
Reset
4 RAM Cells
(NMOS + PMOS)
All-NMOS Comparator
NMOS Latch and Bus Driver
VERTEX 2006
Bus DAC
Detector Capacitance
The large detector capacitance limits the performances of the detector
C(N-well/P-sub) ~ 38 fF
C(N-well/P-well) = 180 fF!
VERTEX 2006
Test-Chip Scheme
Test pulse
Disable
Load DAC
Bias DACs
Select
Mux + shift register
Reset
#2
DAC bits
Sensor Electronic
Mux + shift register
Digital output
VERTEX 2006
ToT output
Noise (Theory)
RB
CF ~ 2.2 fF
RF ~ 0.79 G
CZ ~ 22 fF
RZ ~ 0.060 G
CFOLL ~ 7.6 fF
RFOLL ~ 0.056 G
F
CF
RF
Z
CZ
Cinj
FOLL
Comparator
RFOLL
CSA
RZ
~Sn(RF
~Sn(CDET)2
)2
Z F FOLL

Input current noise (spectral power density)
VERTEX 2006
CFOLL
Z F FOLL
Input transistor noise (SPD)

Noise (Measurements)
120
90
Diode
Regular pixel
Noise vs bias resistance
80
100
80
Regular pixel: 85 e
Diode: 30 e
60
Noise/e
Noise/e
70
60
50
40
40
30
20
1
2
3
4
5
6
7
8
0
9
50
100
150
200
250
300
I bias res./pA
Ampl. bias/A
90
36
Noise vs feedback resistance (RF)
34
80
Noise vs. reverse bias voltage
70
Noise/e
Noise/e
32
30
28
26
0
10
20
30
40
Reverse voltage/V
VERTEX 2006
50
60
I bias res = 260 pA
60
50
I bias res = 130 pA
40
I bias res = 0
0
2
4
6
GFB/nSi
8
10
12
Threshold Dispersion
Tuned
Raw
18
16
16
Sigma: 1.1mV
Mean: 1.250V
14
14
Number of pixels
Number of pixels
927e
1544e
18
20
12
Sigma: 75e
Mean: 830e
10
8
6
4
2
Sigma: 0.75mV
Mean: 1.261V
12
10
8
6
4
2
0
0
500
1000
1500
2000
2500
Threshold/e
Measured sigma of 75 e
VERTEX 2006
3000
3500
0
1,248
1,250
1,252
1,254
1,256
1,258
1,260
1,262
1,264
Threshold/V
Dispersion of tuned thresholds remains unchanged
Time over Threshold
1600
ToT Calibration
1400
1200
Output signal
Threshold
ToT/Clk
1000
800
600
400
200
0
Time over threshold
0,0
0,5
1,0
1,5
2,0
2,5
Input Signal/V
Fit-function:

 Signal  
  1  
ToT    ln  exp 


 

VERTEX 2006
3,0
Fe-55
1400
0,040
Fe-55, Diode, 55V
Hit probability
Number of hits
Regular pixel
0,030
1000
800
600
400
0,025
0,020
0,015
0,010
200
0,005
0
0,000
0
50
100
150
200
250
300
0
ToT/Clk
0,0020
20
40
60
80
100 120 140 160 180 200
ToT/Clk
0,0014
0,0018
Fe-55, 50V
Fe-55, Diode
0,0016
0,0012
0,0012
0,0010
0,0008
0,0006
2V
50V
0,0010
Hit probability
Regular pixel
Diode
0,0014
Hit probability
Fe-55, Regular pixel
55V
0,035
Diode
1200
0,0008
0,0006
0,0004
0,0004
0,0002
0,0002
0,0000
0,0000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Signal/e
VERTEX 2006
0
200 400 600 800 1000 1200 1400 1600 1800 2000
Signal/e
Decrease of
depleted zone
reflects in the
smaller peak
Spectra of the Sr-90 and Co-60
Sr-90
2.283 MeV
(0.935 MeV)
0.546 MeV
(0.196 MeV)
Co-60
1.333 MeV 0.316 MeV
1.173 MeV
L=450 m
VERTEX 2006
Filtering of low-energy Electrons (Sr-90)
(0.935 MeV)
0.546 MeV
Plastic
1.9 mm
(2-2.1 MeVcm2/g)
2 mm
=0.9 g/cm3
(~0.57 MeV)
Si
0.7 mm
(1.6-1.9 MeVcm2/g)
(MIP: 1.5 MeVcm2/g)
=2.3 g/cm3
(~0.28 MeV)
VERTEX 2006
Sr-90
180
400
160
Number of hits
350
300
ToT/Clk
Sr-90, Regular pixel, 55V
200
Calibration
450
a)
b)
220
500
250
200
150
140
120
80
60
100
40
50
20
0
MIP Signal:
2000e/1.17 = 1710 e
Low energy peak:
1.080 e
100
0
0
1000 2000 3000 4000 5000 6000 7000 8000 9000 10000
0
100
200
300
Signal/e
400
500
600
700
800
700
800
ToT/Clk
1,1
Regular pixel, 55V
1,0
0,9
Fe-55
Sr-90
~hit probability
0,8
a)
0,7
0,6
0,5
0,4
0,3
0,2
b)
0,1
0,0
0
100
200
300
400
ToT/Clk
VERTEX 2006
500
600
Bias Voltage and Co-60
High energy peak moves to lower energies
when bias voltage decreases
0,0050
0,0045
Co-60, Diode #2, 60V
0,0040
Hit probability
0,0035
0,0030
0,0025
0,0020
0,0015
0,0010
0,0005
0,0000
0
100 200 300 400 500 600 700 800 900 1000
ToT/Clk
0,0050
0,0050
0,0045
0,0045
Co-60, Diode #2, 0V
0,0040
0,0040
0,0035
0,0035
Hit probability
Hit probability
Co-60, Diode #2, 30V
0,0030
0,0025
0,0020
0,0015
0,0030
0,0025
0,0020
0,0015
0,0010
0,0010
0,0005
0,0005
0,0000
0,0000
0
100 200 300 400 500 600 700 800 900 1000
ToT/Clk
VERTEX 2006
0
100 200 300 400 500 600 700 800 900 1000
ToT/Clk
Bias Voltage and Co-60
High energy peak moves to lower energies
when the bias voltage decreases
0,0050
0,0045
Co-60, Diode #2, 60V
0V
30V
0,0040
Hit probability
0,0035
0,0030
0,0025
0,0020
0,0015
0,0010
0,0005
0,0000
0
100 200 300 400 500 600 700 800 900 1000
ToT/Clk
VERTEX 2006
Fe-55 Image
The matrix was tuned, mean threshold at about 830 e
Fe - 55
Shadow of a wire
Shadow of a micrometer
500,0
800,0
475,0
750,0
450,0
700,0
425,0
650,0
600,0
400,0
375,0
350,0
550,0
500,0
450,0
325,0
300,0
275,0
400,0
250,0
350,0
225,0
300,0
200,0
250,0
175,0
200,0
150,0
150,0
100,0
125,0
100,0
75,00
50,00
0
50,00
25,00
0
VERTEX 2006
Co-60 Irradiation
Pixels at the matrix edges sense more signals
than the inner pixels
2200
2140
2080
2020
1960
1900
1840
1780
1720
1660
1600
1540
1480
1420
1360
1300
1240
1180
1120
1060
1000
VERTEX 2006
Summary
 The idea:
- The use of reverse biased N-well/P-substrate diode as sensor
- Depleted zone of ~ 9 m can be induced by applying of relatively high bias voltage
- CMOS pixel electronics can been implemented in the sensor cathode (N-well)
 The first test-chip have been implemented in a 0.35 m HV CMOS Process
 The pixel electronics comprises
-
Charge sensitive amplifier and CR-RC shaper
Continuous reset and bias
Threshold discrimination with 4-bit tune DAC
NMOS-based latch and bus driver
 Various electrical test demonstrate fully functionality of the detector
 The average MIP signal estimated from the measurements with Sr-90 radioactive sources is
1710 e – it is by far more than expected; probably due to collection of the signal from bulk
 Noise is about 80 e
 Threshold dispersion is 75 e
 Test-beam measurement has to be done; from the presented results I expect good
efficiency of the detector
 New submission with different test matrices is planned
VERTEX 2006
Thank you for your attention
VERTEX 2006
Future Plans (pulsed Reset and DKS)
Reset
Sample
CSA
TCA
AC Coupling
Simpler designs,
which lead to smaller
detector capacitance,
has to be tested
VERTEX 2006
Readout Bus
Standard MAPS
The use of epi layer (or low-ohmic substrate) as sensor
- Charge collection mainly through diffusion
- very low sensor capacitance
Only NMOS transistors in the pixel
Amplified signal
N-well
Epi-layer
Substrate
VERTEX 2006
Triple-Well MAPS
The use of epi layer (or low-ohmic substrate) as sensor and deep N-well as collecting electrode
- Charge collection mainly through diffusion
- Higher sensor capacitance
CMOS electronics in pixel…
but PMOS transistors are placed in the separate N-well
N-well
Epi-layer
Substrate
VERTEX 2006
MAPS in HV Technology
The use of high-voltage N-well/P-substrate diode as sensor
-
Relatively large depleted zone with strong electric field
Efficient charge collection
Fast signals
Better radiation tolerance
Fully implementation of CMOS electronics inside the sensor cathode thanks to triple well option
- Large cathode area but…
moderate capacitance due to thick depleted areas
VERTEX 2006
Capacitances - Simulation
110
10
Deep nwell capacitance vs reverse bias
2
Nwell area ~ 50X50 m
100
Depleted layer thickness vs reverse bias
9
90
Thickness/um
Capacitance/fF
8
80
70
60
7
6
5
50
4
40
3
30
0
10
20
30
40
50
60
0
10
20
30
40
50
Voltage/V
Voltage/V
350
P-well capacitance vs its reverse bias
Capacitance/fF
300
250
200
150
This can be potentially useful!
100
0
5
10
15
Reverse bias/V
VERTEX 2006
20
25
60
Small-Signal Measurements
Time over threshold distribution after many injections
600
260
550
240
600e, regular pixel
220
500
360 e, diode
450
180
Number of signals
Number of signals
200
160
140
120
100
80
60
400
350
300
250
200
150
40
100
20
50
0
0
0
50
100
150
200
ToT/Clk
Regular pixel, 600 e
VERTEX 2006
250
300
0
50
100
150
200
ToT/Clk
Diode, 360 e
250
300
Noise Specification
Undetected Signal
Signal Amplitude
Too high threshold
Noise
6 noise + 6 threshold
Threshold j
Threshold i
Threshold Dispersion
Too low threshold
Noise
Base Line
Noise Hit
6 noise + 6 threshold < Signal
VERTEX 2006
Hit Multiplicity
Larger range of Co-60 signals respecting to Fe-55
1,0
Distribution of multiple hits
~ Probability
0,8
Fe-55
Co-60
0,6
0,4
0,2
0,0
1
2
3
4
5
6
7
Number of pixels hit
VERTEX 2006
8
9
10