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Computer Engineering of Wave Machines for
Seismic Modeling and Seismic Migration
R. Phillip Bording
February 15, 2004
Husky Energy Chair in Oil and Gas Research
Memorial University of Newfoundland
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Max Address
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Session 1
History of Design
Tyco Brahe
Napier
Charles Babbage – mechanical design
John Atanasoff – Storage – spinning capacitor
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Konrad Zuse - Floating Point
Mauchley and Ekert
von-Neumann
Harvard memory – code
memory - data
Princeton
memory code and data
Session 2
Current Design Issues
Scaling laws
Moore’s Law
Transistors – VLSI
Memory – Technology
Division of Design
The memory Challenge
The processor Challenge
The ILLIAC – PEPE
IBM 7094
IBM 360/44
IBM 360/95
Array Processors
the software of array processor calls
Application
Specific
Machines
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Computing and
Calculating Engines
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Session 1
History
Vector memory
Pipeline Arithmetic – Array Processing
Vector memory
Benchmark Driven Dollars

Fairhair Syndrome
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Processors
Data Memory
Alu
Hardwired instructions
Processor Bottleneck
Memory Bottleneck
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Vacuum tubes
Core
Plated Wire
Transistors
LSI – 6 T Static
VLSI - 2 T Dynamic
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Linear Address Space
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Max Address
Address Pointer
Latency is the time to access the first word
Bandwidth is the rate of accessing successive words
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von Neumann
Architecture
Princeton
Address Pointer
Arithmetic
Logic
Unit
(ALU)
Data/Instructions
Memory
Pc = Pc + 1
Program Counter
Featuring Deterministic Execution
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After Gustfason 2004
Bednar, 2004
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Bank memory design
Duplicate memory system
One design for subsystem
 Use a binary tree design to spread out
addresses and data
 Fetch/Store many words at once
 Assume a sequential addressing pattern
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Bank memory design
The wires created a big switch between
modules
The slower memory access time was
better matched to the faster processor
times
 Costly to build – significant effort in
engineering
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Bording
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Array memory design
N rows
NxN bits
N columns
M bits on Bus
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Array memory design
Streaming data flow, nibbles, bytes, and
words
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Sequential Access
First word access time = add+latency+data
 Successive words = data
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Random Access
Indirect Addressing
 Non-uniform Strides
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Benchmark
Scalar operations
Array operations
Do loop domination of codes
Vendors look seriously at instruction
stream
Then comes Linpack. LU decomposition

If it does matrix multiply fast nothing else
matters or does it???
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Bording
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Fairhair Syndrome
New world class machine is designed at MIT,
Stanford, or Caltech
Venture Capital flows in
Federal Government buys 10 new machines
Company goes public
Vulture capitalists sell out
Federal Government buys new machines
from someboldy else -- the next fairhair
Company has stock scandal – goes bankrupt
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Bording
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Session 2
Current Design Issues
Scaling laws
Moore’s Law
Transistors – VLSI
Memory – Technology
Division of Design
The memory Challenge
The processor Challenge
The ILLIAC – PEPE
IBM 7094
IBM 360/44
IBM 360/95
Array Processors
the software of array processor calls