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Ratioed Logic VDD Resistive Load VDD Depletion Load RL PDN VSS (a) resistive load PMOS Load VSS VT < 0 F In1 In2 In3 VDD F In1 In2 In3 PDN VSS (b) depletion load NMOS F In1 In2 In3 PDN VSS (c) pseudo-NMOS Goal: to reduce the number of devices over complementary CMOS Ratioed Logic VDD • N transistors + Load Resistive Load • VOH = V DD RL • VOL = F In1 In2 In3 RPN RPN + RL • Assymetrical response PDN • Static power consumption VSS • tpL= 0.69 RLCL Active Loads VDD Depletion Load VDD PMOS Load VT < 0 VSS F In1 In2 In3 PDN VSS depletion load NMOS F In1 In2 In3 PDN VSS pseudo-NMOS Load Lines of Ratioed Gates IL(Normalized) 1 Current source 0.75 0.5 Pseudo-NMOS Depletion load 0.25 Resistive load 0 0.0 1.0 2.0 3.0 Vout (V) 4.0 5.0 Pseudo-NMOS VDD A B C D F CL VOH = VDD (similar to complementary CMOS) 2 V OL kp 2 k n VDD – V Tn V OL – ------------- = ------ V DD – VTp 2 2 kp V OL = VDD – V T 1 – 1 – -----(assuming that V T = V Tn = VTp ) kn SMALLER AREA & LOAD BUT STATIC POWER DISSIPATION!!! Pseudo-NMOS NAND Gate VDD GND Improved Loads VDD M1 Enable M2 M1 >> M2 F A B C D Adaptive Load CL Improved Loads (2) VDD M1 VDD M2 Out A A B B Out PDN1 PDN2 VSS VSS Dual Cascode Voltage Switch Logic (DCVSL) Example Out Out B B A B B A XOR-NXOR gate
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