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EEE 421 VLSI Circuits
VLSI Circuits
Introduction
ABM H Rashid
CMOS Properties

Full rail-to-rail swing  high noise margins
» Logic levels not dependent upon the relative device
sizes  transistors can be minimum size  ratioless
Always a path to Vdd or GND in steady state 
low output impedance (output resistance in k
range)  large fan-out (albeit with degraded
performance)
 Extremely high input resistance (gate of MOS
transistor is near perfect insulator)  nearly
zero steady-state input current
 No direct path steady-state between power and
ground  no static power dissipation
 Propagation delay function of load capacitance
resistance of transistors
ABM H Rashid
VLSIand
Circuits
Introduction

Transforming PMOS I-V Lines

Want common coordinate set Vin, Vout, and IDn
IDn
IDSp = -IDSn
VGSn = Vin ; VGSp = Vin - VDD
VDSn = Vout ; VDSp = Vout - VDD
Vout
Vin = 0
Vin = 0
Vin = 1.5
Vin = 1.5
VGSp = -1
VGSp = -2.5
VLSI Circuits
Mirror around x-axis
Vin = VDD + VGSp
IDn = -IDp
Introduction
Horiz. shift over VDD
Vout = VDD + VDSp
ABM H Rashid
CMOS Inverter Load Lines
PMOS
2.5
NMOS
X 10-4
Vin = 0V
Vin = 2.5V
2
Vin = 0.5V
Vin = 2.0V
1.5
Vin = 1.0V 1
Vin = 2V
0.5
Vin = 1V
Vin = 1.5V
Vin = 1.5V
Vin = 0.5V
Vin = 1.5V
Vin = 1.0V
Vin = 2.0V
Vin = 0.5V
0
Vin = 2.5V 0
0.5
1
1.5
Vout (V)
2
2.5 Vin = 0V
0.25um, W/Ln = 1.5, W/Lp = 4.5, VDD = 2.5V, VTn = 0.4V, VTp = -0.4V
VLSI Circuits
Introduction
ABM H Rashid
Vout (V)
CMOS Inverter VTC
2.5
2
1.5
1
0.5
0
NMOS off
PMOS res
NMOS sat
PMOS res
NMOS sat
PMOS sat
NMOS res
PMOS sat
0
0.5
1
1.5
2
NMOS res
PMOS off
2.5
Vin (V)
VLSI Circuits
Introduction
ABM H Rashid