Download No Slide Title

CMOS INVERTER
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
DIGITAL GATES
Fundamental Parameters




Functionality
Reliability, Robustness
Area
Performance
» Speed (delay)
» Power Consumption
» Energy
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
The Ideal Gate
Vout
Ri = 
Ro = 0
g= 
Vin
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
VTC of Real Inverter
Vout (V)
4.0
VTL
2.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
Vin (V)
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
The CMOS Inverter:
A First Glance
VDD
Vin
Vout
CL
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
CMOS Properties





Full rail-to-rail swing
Symmetrical VTC
Propagation delay function of load
capacitance and resistance of transistors
No static power dissipation
Direct path current during switching
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Voltage Transfer
Characteristic
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
PMOS Load Lines
IDn
V in = V DD -VGSp
IDn = - IDp
V out = VDD -VDSp
V out
IDp
IDn
IDn
Vin=0
Vin=0
Vin=3
Vin=3
V DSp
V DSp
Vout
VGSp=-2
VGSp=-5
Elettronica T A.A. 2010-2011
Vin = V DD+VGSp
IDn = - IDp
Inverter
Vout = V DD+VDSp
Digital Integrated Circuits © Prentice Hall 2003
CMOS Inverter Load Characteristics
IDS,n
Vin = 5
V in = 0
NMOS
PMOS
Vin = 4
Vin = 1
Vin = 4
Vin = 3
Vin = 2
Vin = 3
Vin = 4
Vin = 2
V in = 3
Vin = 1
Vin = 0
Vin = 5
Elettronica T A.A. 2010-2011
Vin = 2
Inverter
Digital Integrated Circuits © Prentice Hall 2003
CMOS Inverter VTC
NMOS off
PMOS lin
5
Vou t
4
NMOS sat
PMOS lin
2
3
NMOS sat
PMOS sat
1
NMOS lin
PMOS sat
1
Elettronica T A.A. 2010-2011
2
Inverter
3
4
NMOS lin
PMOS off
5
Vin
Digital Integrated Circuits © Prentice Hall 2003
Simulated VTC
Vout (V)
4.0
2.0
0.0
0.0
1.0
2.0
3.0
4.0
5.0
Vin (V)
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Gate Switching Threshold
4.0
VM
3.0
2.0
1.00.1
Elettronica T A.A. 2010-2011
0.3
1.0
kp/kn
Inverter
3.2
10.0
Digital Integrated Circuits © Prentice Hall 2003
Impact of process variations
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
VIH, VIL and gain
VM
VIH  VM 
g
V  VM
VIL  VM  DD
g
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Propagation Delay
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Computing CMOS inverter
delay in the quadratic model
VDD
Vin
Vout
Vout
CL
VDD
Vdd - VTN
t
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Computing CMOS inverter
delay in the linear model
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = VDD
RonCL
Elettronica T A.A. 2010-2011
Inverter
t
Digital Integrated Circuits © Prentice Hall 2003
NMOS/PMOS ratio
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Impact of Rise Time on Delay
0.35
tpHL(nsec)
0.3
0.25
0.2
0.15
Elettronica T A.A. 2010-2011
0
0.2
0.4
0.6
trise (nsec)
Inverter
0.8
1
Digital Integrated Circuits © Prentice Hall 2003
Delay as a function of VDD
28
Normalized Delay
24
20
16
12
8
4
0
1.00
2.00
3.00
4.00
5.00
VDD (V)
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Power Consumption
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Where Does Power Go in CMOS?

Dynamic Power Consumption
» Charging and Discharging Capacitors

Short Circuit Currents
» Short Circuit Path between Supply Rails during Switching

Leakage
» Leaking diodes and transistors
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Short circuit current
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Minimizing SC Power
Keep the input and output fall time the same
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Leakage (static) power
Sub-threshold current is one of the most
Compelling issues in low-energy design
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Reverse-biased diode leakage
JS=JSA
 JS=1-5pA/µm2 in 1.2µm CMOS
 JS doubles with every 90C in T

Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003
Sub-threshold leakage
Elettronica T A.A. 2010-2011
Inverter
Digital Integrated Circuits © Prentice Hall 2003