Download Slide 1

VLSI Design Flow
RTL (in HDL)
Logic Synthesis
Netlist
Physical Design
Layout
CprE566 / Fall 06 / Prepared by Chris Chu
Introduction to VLSI Design and Physical Design
1
Full Scaling of MOS Transistors
W
G
S
Xj
tox
Leff
D
B
Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET).
The main dimensions that determine device properties are gate oxide thickness
tgox; gate length L, gate width W; and junction depth Xj
• All horizontal & vertical dimensions of a
transistor (W, L, tox, Xj) are reduced by S
• All voltages (VDD, VTN, VTP) are reduced by S
• Substrate doping (Nsub) is increased by S
2
Simple Scaling
Constant
Full
Voltage
Scaling
Scaling
Parameter
Dimensions:
width, length, oxide thickness
Voltages:
supply, threshold
Intrinsic gate delay
Gate Capacitance
Current per device
Power dissipation per gate
CprE566 / Fall 06 / Prepared by Chris Chu
1/S
1/S
1/S
1
1/S
1/S
1/S
1/S2
1/S2
1/S
S
S
Introduction to VLSI Design and Physical Design
3
Ideal Scaling of VLSI Interconnects
Wsp
Lint
Wint
Hint
Tox
Basic interconnection parameters
• Cross Sectional dimensions ( Wint, Hint, Wsp, Tox)
are reduced by S
• Die Size and global interconnection lengths are
increased by Sc
4
Scaling of Local and Global
Interconnects
Parameter
Scaling Factor
Cross sectional Dimensions (W int , H int , W sp, t ox )
1/S
1
)
Wi ntHi nt
S2
W int
)
tox
1
Resistance per unit length (R i nt = ρi nt
Capacitance per unit length (C int = eox
RC constant per unit length (R int C int )
S2
Local interconnection length (l loc )
1/S
2
Local interconne ction RC delay (RintCintlloc
)
1
Die size (D C )
SC
Global interconnection length (l int )
SC
2
Global interconne ction RC delay (RintCintl int
)
S2(SC)2
Transistor line time of flight (l int /v c )
SC
(Fringing and coupling capacitances are neglected)
Intrinsic gate delay scaled by 1/S for full scaling.
5
Interconnect vs. Gate Delay
40
Interconnect Delay
Gate Delay
35
Delay (ps)
30
25
Metal: Al
Dielectric:
SiO2
20
15
10
5
0
0.65
0.5
1989
1992
0.35
1995
0.25
0.18
0.13
0.1
1998
2001
2004
2007
Technology Generation(mm)
Source: NTRS’97
6
Interconnect vs. Gate Delay
40
Interconnect Delay
Gate Delay
35
Delay (ps)
30
25
20
Metal: Cu
Dielectric: low k
15
10
5
0
0.65
0.5
1989
1992
0.35
1995
0.25
0.18
0.13
0.1
1998
2001
2004
2007
Technology Generation(mm)
Source: NTRS’97
7
Interconnects – Why do we care? (1)
ITRS 2001
8
Solutions to Interconnect Delay
• Dominating factor in determining circuit performance
nowadays.
• Solutions:
– Copper wire
– Low-k (dielectric constant) material
– Placement of devices and routing of interconnects become
critical
– Interconnect optimization (e.g., driver sizing, buffer insertion,
wire sizing) at physical design
– Consider effects of interconnect delay during synthesis (i.e.,
physical synthesis)
9