Download A 312GHz fourth-harmonic voltage

A 0.8-13.4GHz combined differential
voltage-controlled oscillator
with an exclusive-OR
in 130nm SiGe BiCMOS
Yang Lin and David E. Kotecki
Electrical and Computer Engineering Department
University of Maine, USA
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
1
Outline
 Wide-tuning voltage-controlled oscillator (VCO) applications
 Previous work on the state-of-the-art wide-tuning VCOs
 Design & Post-layout simulation of this work
 The differences between this design & previous presentation
Lower power
Smaller size
Differential outputs
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
2
Voltage-Controlled Oscillator (VCO)
Vdd
Vtune
Vtune controls
output frequency
VCO
Load
Gnd
Gnd
fmin
fmin
fmax
fmax
Differential VCO
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Wide-tuning VCO applications
Communication
UWB Application
(3.1-10.6GHz by Federal
Communications Commission (FCC))
Radar
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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State-of-the-art wide-tuning VCOs
Frequency
(GHz)
Output
Type
Topology
1-9
Quadrature Two-stage VCO
1.82-10.18
Differential Two-stage digitally controlled CMOS 130nm
3-10
Single
1-10
Differential Four-stage VCO
CMOS 90nm
0.23-6.3
Differential Relaxation VCO
CMOS 90nm
0.1-65.8
Single
Triple-push with lumped
devices
CMOS 90nm
3-11
Single
Coupled two-stage
CMOS 180nm
1.25-13.66
Differential QVCO + two stages XOR
Digitally-controlled ring
Presentation 1 2.9-30.3
Single
This work
Differential QVCO + XOR
Dec.12-15, 2010
0.8-13.4
Technology
CMOS 130nm
CMOS 90nm
AlGaAs/GaAs
QVCO + XOR +
BiCMOS SiGe
push-push frequency doubler 130nm
BiCMOS
SiGe 130nm
5
17th IEEE International Conference on Electronics, Circuits and Systems
Architecture
f0
0.4-6.7GHz
Ring
Quadrature
VCO
Ap
An
Bp’
Bn’
2f0
0.8-13.4GHz
Ap
An
BiCMOS Zp
Gilbert Zn
XOR
Bp
Bn
50 Ohm
50 Ohm
 For the XOR,
differential inputs Ap and An (0o delay @ frequency f0 )
XOR differential inputs Bp and Bn (90o delay @ frequency f0)
=
differential outputs Zp and Zn (frequency 2f0 )
1
0
 Base-collector-connected (level-shifting) NPN transistors:
decrease the XOR input voltages for Bp and Bn
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Ring VCO
VCO Types
Advantages
Disadvantages
Ring VCO
Wider tuning range,
smaller core area
Lower operating frequency
Poorer phase noise
LC-tank VCO Higher frequency,
better phase noise (high-Q)
Limited tuning range,
large area, high cost
Vtune
0
Delay Cell
1
1
Delay Cell
0
0
Delay Cell
Delay Cell
1
0
1
output
output
Ring VCO with differential delay cells
Single-ended: odd delay cells
Differential: odd/even delay cells
Dec.12-15, 2010
N: number of delay cells
Tp: propagation time through each delay cell
Period T=2NTp
17th IEEE International Conference on Electronics, Circuits and Systems
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Ring Quadrature VCO (QVCO)
inp
Delay
Cell
inn
inp
Delay
Cell
inn
outp
Buffer
0o
outn
Buffer
180o
outp
Buffer
90o
outn
Buffer
270o
Ap
An
Bp’
Bn’
Delay cell
Gate width/length (µm)
Buffer: Common source (amplified output)
‘Vctrl’ is high: low-frequency mode, T1 & T4 close to ‘off’, T2 & T3
provide most currents
‘Vctrl’ achieves a specific high value, the oscillation freq. keeps the same
‘Vctrl’ is low: high-frequency mode, |Vgs| of T1 & T4 increases,
current and freq. boost
Increasing ‘Vdd’ boosts the output frequency
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
8
BiCMOS Gilbert XOR
Logic Part
Current
Source
Emitter followers as buffers
A
B
A XOR B
Ap<An(0)
Bp<Bn(0) Zp<Zn(0)
Ap<An(0)
Bp>Bn(1)
Ap>An(1)
Bp<Bn(0) Zp>Zn(1)
Ap>An(1)
Bp>Bn(1)
Zp>Zn(1)
Zp<Zn(0)
Logic part, Emitter followers & Current source
Delays of Ap, An, Bp and Bn are 0o, 180o, 90o and 270o
Bp & Bn are ~0.7V lower than Ap & An
Zp and Zn are differential outputs
BiCMOS XOR outperforms CMOS XOR: high frequency & differential outputs
CMOS XOR: up to ~5.5GHz input freq.
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Microchip Layout
QVCO
450µm
XOR
450µm
The ground & power planes are not shown for clarity.
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Post-layout simulation results
Oscillation Frequency
13.4GHz
Tuning range = 177%
0.8GHz
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Max frequencies @ different temperatures
13.889GHz
Temperature coefficient
~ -12.5MHz/oC
12.889GHz
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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VCO transient differential outputs
@13.4GHz into 50Ω loads
•Non-ideally symmetrical 2ndharmonic output signals
• Peak-peak voltage amplitude
~30mV
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Output power spectrum into a 50Ω load
13.4 GHz, -30 dBm
The rejections
29dB @6.5GHz
28dB @19.5GHz
19dB @26GHz
@13.4 GHz, Dissipated power: 15.52 mW, Output power: -30 dBm
@0.8 GHz, Dissipated power: 13.98 mW, Output power: -45 dBm
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Phase Noise (PN) versus offset frequency
At 10MHz offset frequency,
PN= -91.5 dBc/Hz @ 13.4GHz oscillation frequency
PN= -100.1 dBc/Hz @ 0.8GHz oscillation frequency
13.4GHz oscillation frequency,
-91.5 dBc/Hz @10MHz offset frequency
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Conclusions
 A ring QVCO + An XOR
 Tuning range : 0.8 to 13.4 GHz (177%)
 Dissipated power: [email protected], [email protected]
Output power into 50 Ohm loads: [email protected],
[email protected]
 Phase Noise : 10MHz offset frequency,
-91.5 dBc/Hz @ 13.4GHz oscillation freq.
-100.1 dBc/Hz @ 0.8GHz oscillation freq.
 Microchip area : 450µm×450µm
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Comparison
VCOs
This design (Presentation 5)
Previous presentation
(presentation 1)
Topology
Ring QVCO + XOR
Ring QVCO + XOR
+ Push-push frequency doubler
Performance
The widest tuning range in the
130nm ring VCOs reported
Advantages
Small chip area (450µm×450µm)
Low power dissipation (~14mW)
Differential outputs
High frequency (2.9-30.3GHz) with
4f0
Disadvantages
Low frequency (0.8-13.4GHz) with
2fo
Large chip area (750µm×500µm)
High power dissipation (~33mW)
Single output
Q: Why 2.9-30.3GHz is not exactly twice of 0.8-13.4GHz?
A: different parameters, different applied voltage ranges to ensure oscillation
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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Thank you very much!
Dec.12-15, 2010
17th IEEE International Conference on Electronics, Circuits and Systems
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