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COMBINATIONAL
LOGIC
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Combinational vs. Sequential Logic
In
Logic
In
Circuit
Out
Logic
Out
Circuit
State
(a) Combinational
(b) Sequential
Output = f(In, Previous In)
Output = f(In)
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Static CMOS Circuit
At every point in time (except during the switching
transients) each gate output is connected to either
VDD or Vss via a low-resistive path.
The outputs of the gates assume at all times the value
of the Boolean function, implemented by the circuit
(ignoring, once again, the transient effects during
switching periods).
This is in contrast to the dynamic circuit class, which
relies on temporary storage of signal values on the
capacitance of high impedance circuit nodes.
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
NMOS Transistors in
Series/Parallel


Primary inputs drive both gate and source/drain
terminals
NMOS switch closes when the gate input is high
A
B
X = Y if A and B
X
Y
A
X = Y if A or B
B
X

Y
Remember - NMOS transistors pass a strong 0 but a
weak 1
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
PMOS Transistors in
Series/Parallel


Primary inputs drive both gate and source/drain
terminals
PMOS switch closes when the gate input is low
A
B
X
Y
X = Y if A and B = A + B
A
X

B
X = Y if A or B = A  B
Y
Remember - PMOS transistors pass a strong 1 but a
weak 0
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Threshold Drops
VDD
PUN
VDD
S
D
VDD
D
0  VDD
VGS
S
CL
CL
VDD  0
PDN
D
VDD
CL
S
Elettronica T A.A. 2010-2011
0  VDD - VTn
VGS
VDD  |VTp|
S
CL
D
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Static CMOS
VDD
In1
In2
In3
PUN
PMOS Only
F=G
In1
In2
In3
PDN
NMOS Only
VSS
PUN and PDN are Dual Networks
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Example Gate: NAND
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Example Gate: NOR
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Example Gate: COMPLEX CMOS GATE
VDD
B
A
C
D
OUT = D + A• (B+C)
A
D
B
Elettronica T A.A. 2010-2011
C
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Complex Gate Synthesis

Pulldown networks
» series-connected transistors or subnetworks
implement AND functions
» parallel transistors or subnetworks implement OR functions

Pullup networks
» series-connected transistors or subnetworks
implement OR functions
» parallel transistors or subnetworks implement AND functions

Can be designed directly from the logic expression
the gate is to implement
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
F=[A(B+C)]’


F = NOT(AND(A, OR(B+C))
Pulldown network: [A(B+C)]’
A
B
C
» AND(A, OR(B, C)) is implemented
as series-connected a transistor
and a subnetwork OR(B+C)
» OR(B+C) is implemented with parallel transistors

Pullup network: [A(B+C)]’
» AND(A, OR(B, C)) is implemented
as parallel connection of a transistor
and a subnetwork OR(B, C)
» OR(B, C) is implemented
with series-connected transistors
Elettronica T A.A. 2010-2011
Combinational Logic
B
A
C
Digital Integrated Circuits © Prentice Hall 2003
F=[A(B+C)]’ (cont’d)
Vdd
B
A
C
F
A
B
C
GND
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Complementary CMOS Logic Style Construction
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Properties of Complementary CMOS Gates
High noise margins:
VOH and VOL are at VDD and GND, respectively.
No static power consumption:
There never exists a direct path between VDD and
VSS (GND) in steady-state mode.
Comparable rise and fall times:
(under the appropriate scaling conditions)
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Transistor Sizing
• for symmetrical response (dc, ac)
• for performance
VDD
B
12
C
12
6
A
Input Dependent
Focus on worst-case
D
6
F
A
D
2
1
B
Elettronica T A.A. 2010-2011
2 C
2
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Propagation Delay Analysis - The Switch
Model
RON
=
VDD
VDD
Rp
Rp
A
B
F
F
A
CL
Rn
B
Rp
CL
Rn
A
(a) Inverter
Rp
Rp
B
A
Rn
VDD
(b) 2-input NAND
A
F
Rn
Rn
A
B
CL
(c) 2-input NOR
tp = 0.69 Ron CL
(assuming that CL dominates!)
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Analysis of Propagation Delay
VDD
Rp
A
1. Assume Rn =Rp = resistance of minimum
sized NMOS inverter
Rp
B
F
Rn
B
Rn
A
CL
2. Determine “Worst Case Input” transition
(Delay depends on input values)
3. Example: tpLH for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
tpLH = 0.69Rp CL
2-input NAND
4. Example: tpHL for 2input NAND
- Worst case : TWO NMOS in series
tpHL = 0.69(2Rn)CL
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Input Pattern Effects on Delay
Rp
A
Rp
B


Rn
» both inputs go low
CL
– delay is 0.69 Rp/2 CL
B
Rn
Delay is dependent on
the pattern of inputs
Low to high transition
» one input goes low
Cint
A
– delay is 0.69 Rp CL

High to low transition
» both inputs go high
– delay is 0.69 2Rn CL
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Delay Dependence on Input Patterns
3
A=B=10
2,5
Voltage [V]
2
A=1 0, B=1
1,5
A=1, B=10
1
0,5
0
-0,5
0
100
200
300
Delay
(psec)
A=B=01
67
A=1, B=01
64
A= 01, B=1
61
A=B=10
45
A=1, B=10
80
A= 10, B=1
81
NMOS = 0.5m/0.25 m
PMOS = 0.75m/0.25 m
CL = 100 fF
time [ps]
Elettronica T A.A. 2010-2011
400
Input Data
Pattern
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Design for Worst Case
V DD
VDD
1
A
1
F
2
B
CL
4
C
4
2
A
B
B
D
2
F
A
2
D
A
2
1
B
2C
2
Here it is assumed that Rp = Rn
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
tp as a function of Fan-In
4.0
tpHL
tp (nsec)
3.0
2.0
tp
quadratic
1.0
linear
0.0
1
3
5
fan-in
7
tpLH
9
AVOID LARGE FAN-IN GATES! (Typically not more than FI < 4)
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
tp as a function of Fan-Out
Elettronica T A.A. 2010-2011
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003
Influence of Fan-In and Fan-Out
on Delay
VDD
A
B
C
D
Fan-Out: Number of Gates Connected
2 Gate Capacitances per Fan-Out
A
B
FanIn: Quadratic Term due to:
C
1. Resistance Increasing
2. Capacitance Increasing
(tpHL )
D
t
Elettronica T A.A. 2010-2011
p
= a FI + a FI 2 + a FO
1
2
3
Combinational Logic
Digital Integrated Circuits © Prentice Hall 2003