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Chapter 5
The Inverter
V1. April 10, 03
V1.1 April 25, 03
Inverter
Objective of This Chapter
 Use
Inverter to know basic CMOS
Circuits Operations
 Watch for performance Index such as
 Speed (Delay calculation)
 Optimal Transistor Sizing for speed and
Energy
 Power Consumption and Dissipation
Inverter
The CMOS Inverter: A First Glance
V DD
V in
V out
CL
Inverter
CMOS Inverter
N Well
VDD
VDD
PMOS
Contacts
PMOS
In
Out
In
Out
Metal 1
Polysilicon
NMOS
NMOS
GND
Inverter
Two Inverters
Share power and ground
Abut cells
VDD
Vin
Connect in Metal
Vout
Vout
Vin
Inverter
CMOS Inverter
First-Order DC Analysis
V DD
V DD
Rp
V out
V out
VOL = 0
VOH = VDD
Rn
V in = V DD
V in = 0
Inverter
Delay Definitions
Inverter
CMOS Inverter: Transient Response
V DD
V DD
tpHL = f(R on.CL)
Rp
= 0.69 RonCL
V out
V out
CL
CL
Rn
ln(2)=0.69
V in = 0
V in = V DD
(a) Low-to-high
(b) High-to-low
Inverter
Voltage Transfer
Characteristic
Inverter
PMOS Load Lines
(Vdd = 2.5V in 0.25um CMOS Process)
(Vt = 0.4V as shown in Table 3-2)
IDn
V
+V
DD GS,p
I =-I
D,n
D,p
V
=V
+V
out
DD DS,p
in
=V
V out
IDp
IDn
V
VGSp=-1
IDn
Vin=0
Vin=0
Vin=1.5
Vin=1.5
DS,p
V
DS,p
V
out
VGSp=-2.5
V in = V DD +VGSp
IDn = - I Dp
Vout = V DD +VDSp
Inverter
CMOS Inverter Load Characteristics
ID n
PMOS
Vin = 0
Vin = 2.5
Vin = 0.5
Vin = 2
Vin = 1
Vin = 1.5
Vin = 1.5
Vin = 1
Vin = 1.5
Vin = 2
Vin = 2.5
NMOS
Vin = 1
Vin = 0.5
Vin = 0
Vout
Inverter
CMOS Inverter VTC
NMOS off
PMOS res
2.5
Vout
2
NMOS s at
PMOS res
VM: Vin = Vout
Switching Threshold
Voltage
1
1.5
NMOS sat
PMOS sat
0.5
NMOS res
PMOS sat
0.5
1
1.5
2
NMOS res
PMOS off
2.5
Vin
Inverter
Switching Threshold as a Function of
Transistor Ratio
NMOS and PMOS are in Saturation Modes
VM 
rVDD
( when
1 r
VDD  VDSAT ,VTn ,VTp )
For r = 1, and saturated velocity NMOS = 2 PMOS, Wp = 2Wn
Inverter
Switching Threshold as a Function of
Transistor Ratio
1.8
1.7
1.6
1.5
M
V (V)
1.4
1.3
1.2
1.1
1
0.9
0.8
10
0
10
W /W
p
1
n
Inverter
Simulated VTC
2.5
2
Vout(V)
1.5
1
0.5
0
0
0.5
1
1.5
2
2.5
V (V)
in
Inverter
Impact of Process Variations
2.5
2
Good PMOS
Bad NMOS
Vout(V)
1.5
Nominal
1
Good NMOS
Bad PMOS
0.5
0
0
0.5
1
1.5
2
2.5
Vin (V)
Good: Smaller oxide thickness, smaller L, higher W, smaller VT
Inverter
Propagation Delay
Inverter
CMOS Inverters
VDD
PMOS
1.2mm
=2l
In
Out
Metal1
Polysilicon
NMOS
GND
Inverter
CMOS Inverter Propagation Delay
VDD
tpHL = f(Ron.CL)
= 0.69 RonCL
Vout
ln(0.5)
Vout
CL
Ron
1
VDD
0.5
0.36
Vin = V DD
RonCL
t
Inverter
The Transistor as a Switch
VGS  V T
Ron
S
D
ID
V GS = VD D
Rmid
R0
V DS
VDD/2
VDD
Inverter
The Transistor as a Switch
7
x 10
5
6
Req (Ohm)
5
4
3
2
1
0
0.5
1
1.5
V
DD
2
2.5
(V)
Inverter
The Transistor as a Switch
Inverter
Transient Response
3
2.5
?
Vout(V)
2
tp = 0.69 CL (Reqn+Reqp)/2
1.5
1
0.5
tpHL
tpLH
0
-0.5
0
0.5
1
1.5
t (sec)
2
2.5
-10
x 10
Inverter
Design for Performance
 Keep
loading capacitances (CL) small
 Increase transistor sizes (add CMOS
gain)
 Watch out for self-loading (for the previous
stage)!
VDD (????)  Power
consumption??
 Increase
Inverter
Delay (speed degrade) as a function of VDD
5.5
5
tp(normalized)
4.5
4
3.5
3
2.5
2
1.5
1
0.8
1
1.2
1.4
1.6
V
1.8
2
2.2
2.4
(V)
DD
Inverter
NMOS/PMOS ratio
-11
5
x 10
tpHL
tpLH
tp(sec)
4.5
b = Wp/Wn
tp
4
3.5
3
1
(See pp. 204)
1.5
2
2.5
3
3.5
4
4.5
5
b
Fig. 5-18
Inverter
Device Sizing
-11
3.8
x 10
(for fixed load)
3.6
3.4
tp(sec)
3.2
3
2.8
Self-loading effect:
Intrinsic capacitances
dominate
2.6
2.4
2.2
2
(Fig. 5-19)
2
4
6
8
S
10
12
14
Inverter
Inverter Sizing
Inverter
Inverter Chain
In
Out
1
f1
f2
CL
If CL is given:
- How many stages are needed to minimize the delay?
- How to size the inverters?
May need some additional constraints.
Inverter
Inverter Delay
• Minimum length devices, L=0.25mm
• Assume that for WP = 2WN =2W
• same pull-up and pull-down currents
• approx. equal resistances RN = RP
• approx. equal rise tpLH and fall tpHL delays
• Analyze as an RC network
 WP 

RP  Runit 
 Wunit 
1
 WN 

 Runit 
 Wunit 
Delay (D): tpHL = (ln 2) RNCL
Load for the next stage:
2W
W
1
 RN  RW
tpLH = (ln 2) RPCL
W
C gin  3
Cunit
Wunit
Inverter
Inverter with Load
Delay
RW
2W
W
CL
RW
Load (CL)
tp = k RWCL
•k is a constant, equal to 0.69
•Assumptions: no load  zero delay
Inverter
Inverter with Load and Para. Cap.
CP = 2Cunit
Delay
2W
W
Cint
CL
CN = Cunit
Load
Delay = kRW (Cint + CL) = kRWCint + kRWCL
= kRW Cint(1+ CL /Cint)
= Delay (Internal) + Delay (Load)
Inverter
Delay Formula
Delay ~ RW Cint  C L 
t p  kRW Cint 1  C L / Cint   t p 0 1  f /  
Cint = Cgin with   1
f = CL/Cgin : Effective fanout
RW = Runit / W ; Cint =WCunit
tp0 = 0.69RunitCunit
Inverter
Apply to Inverter Chain
In
Out
1
2
N
CL
tp = tp1 + tp2 + …+ tpN
 C gin, j 1 

t pj ~ RunitCunit 1 
 C

gin
,
j


N
N 
C gin, j 1 
, C gin, N 1  C L
t p   t p , j  t p 0  1 
 C

j 1
i 1 
gin, j 
Inverter
Optimal Tapering for Given N
Delay equation has (N-1) unknowns, Cgin,2 ~ Cgin,N
Minimize the delay, find (N – 1) partial derivatives
Result: Cgin,j+1/Cgin,j = Cgin,j/Cgin,j-1
Size of each stage is the geometric mean of two neighbors
C gin, j  C gin, j 1C gin, j 1
- Each stage has the same effective fanout (Cout/Cin)
- Each stage has the same delay
Inverter
Optimum Delay and Number of Stages
When each stage is sized by f and has same effective
fanout f
f N  F  CL / Cgin,1
Effective fanout of each stage:
f NF
Minimum path delay

t p  Nt p 0 1  N F / 

Inverter
Example
In
C1
Out
1
f
f2
CL= 8 C1
CL/C1 has to be evenly distributed across N = 3 stages:
f 38 2
Inverter
Optimum Number of Stages
For a given load, CL and given input capacitance Cin
Find optimal sizing f
CL  F  Cin  f Cin
N
t p  Nt p 0 F
1/ N
ln F
with N 
ln f
t p 0 ln F  f


/   1 

  ln f ln f
t p
t p 0 ln F ln f  1   f


0
2
f

ln f



f  exp 1   f 
For  = 0, f = e, N = lnF
Inverter
Optimum Effective Fanout f
Optimum f for given process defined by 
f  exp 1   f 
fopt = 3.6
for =1
fopt = 2.718
for =0
Inverter
Normalized delay function of F

t p  Nt p 0 1  N F / 

Inverter
Buffer Design
1
f
tp
1
64
65
2
8
18
64
3
4
15
64
4
2.8
15.3
64
1
8
1
4
16
2.8
8
1
N
64
22.6
Without considering the internal capacitance
Inverter
Power Dissipation
Inverter
Where Does Power Go in CMOS?
• Dynamic Power Consumption
Charging and Discharging Capacitors
• Short Circuit Currents
Short Circuit Path between Supply Rails during Switching
• Leakage
Leaking diodes and transistors
Inverter
Dynamic Power Dissipation
Vdd
Vin
Vout
CL
Energy/transition = CL * Vdd2
Power = Energy/transition * f = CL * Vdd2 * f
Not a function of transistor sizes!
Need to reduce CL, Vdd, and f to reduce power.


2
dvout
CLVDD
EC   iVDD (t )vout dt  CL
vout dt 
dt
2
0
0
Energy in CL
Inverter
Node Transition Activity and Power
Consider switching a CMOS gate for N clock cycles
E N = CL  V dd2  n N 
EN : the energy consumed for N clock cycles
n(N ): the number of 0->1 transition in N clock cycles
EN
2
n N 
P avg = lim --------  fclk =  lim ----------- C  Vdd  f clk
N   N 
N N
L
0  1 =
n N 
lim -----------N N
P avg = 0 1  C  Vdd 2  f clk

L
2
2
PAVG  ( 01  C L ) VDD
 f CLK  C Eff  VDD
 f CLK
(C Eff : Effective Capacitanc e)
Inverter
Switching Activity (Example 5.12)
 01  2 / 8  0.25
Inverter
Transistor Sizing for Minimum Energy

Goal: Minimize Energy of whole circuit while maintaining
the speed speed performance
 Design parameters: f and VDD
 tp  tp,ref of referenced circuit with f=1 and Vdd =Vref
In
Out
Cg1
1
f
Cext

f 
F 
t p  t p 0  1    1   
( F  Cext / C g1 )
f  
   
VDD
t p0 
(VTE  VT  VDSAT / 2)
VDD  VTE
Inverter
Transistor Sizing (2)

Performance Constraint (=1)  Vdd(f)
tp
t pref


t p0
t p 0 ref

F
 2  f  
f  VDD Vref  VTE


3  F 
Vref VDD  VTE

F
 2  f  
f 

1
3  F 
Energy for single transition
2
2
E  VDD
Cg11    f  f  F   VDD
Cg1[(1   )(1  f )  F ]

Energy ratio of the design and reference circuit
2
 VDD ( f )   2  2 f  F 
E
 




Eref  Vref   4  F 
Inverter
Transistor Sizing (4)
VDD=f(f)
E/Eref=f(f)
4
1.5
3.5
normalized energy
3
F=1
vdd (V)
2.5
2
2
5
1.5
1
0.5
1
10
0.5
0
1
2
3
4
5
6
20
7
f
Required Supply Voltage
0
1
2
3
4
5
6
7
f
Energy v.s. Sizing factor
Inverter
Sizing factor for Speed and Energy

Device sizing, combined with supply voltage
reduction, is a very effective way in reducing energy
consumption of a logic network.
 The gain can be up to 10 for large fanout.


Oversizing beyond the optimal value comes at a hefty
price in energy.
Optimal size for energy is smaller than the optimal
sizing for performance.
 For example, f(energy) = 3.53, f(performance) = 4.47= 20 ,
for F=20
Inverter
Short Circuit Currents (during switching)
Vd d
Vin
Vout
CL
IVDD (mA)
0.15
0.10
0.05
0.0
1.0
2.0
3.0
Vin (V)
4.0
5.0
Inverter
Minimizing Short-Circuit Power
Inverter
Neil Weste
Textbook
Inverter
Leakage Current
Vdd
Vdd
Vout = Vdd
Drain Junction
Leakage Current
Sub-Threshold
Current
Sub-threshold current is one of most compelling issues
in low-energy circuit design!!
Inverter
Reverse-Biased Diode Leakage
GATE
p+
p+
N
Reverse Leakage Current
+
V
- dd
IDL = JS  A
2
JSJ= =10-100
pA/mm2
at m25
deg
C for
0.25mm CMOS
1-5pA/
m
for
a
1.2
m
CMOS
technology
m
S
JS doubles for every 9 deg C!
Js double with every 9oC increase in temperature
Inverter
Subthreshold Leakage Component
Inverter
Static Power Consumption
Vd d
Istat
Vout
Vin =5V
CL
Pstat = P(In=1) .Vdd . Istat
• Dominates over dynamic consumption
Wasted energy …
• Not
a function
of switching
frequency
Should
be avoided
in almost
all cases.
Inverter
Principles for Power Reduction

Prime choice: Reduce voltage!
 Recent years have seen an acceleration in supply
voltage reduction
 Design at very low voltages still open question
(0.6, … , 0.9 V by 2010!)

Reduce switching activity (at different levels)

Reduce physical capacitance
 Device Sizing: for example, for F = 20
fopt(energy)=3.53, fopt(performance)=4.47.
Inverter