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FUTURE NANOELECTRONIC
DEVICES AND THEIR
APPLICATIONS
Larry Cooper
Arizona State University
Future Directions in CAS: A Day of Brainstorming
May 27, 2005, Kobe, Japan
NANOELECTRONIC DEVICES AND THEIR
APPLICATIONS
BASIC CONCEPT
LOW POWER (1000X)
+ HIGH SPEED (100X)
+ARCHITECTURE
=NEW FUNCTIONALITIES
“BEYOND SILICON”
“BEYOND SILICON”
COMPOUND SEMICONDUCTORS
FERROMAGNETIC METALS AND SEMICONDUCTORS
_________________
DEVICES ARE IN THE EXPLORATORY PHASE
A MEASUREABLE PROPERTY IS OBSERVED WHICH CAN BE CONTROLLED
WITH CURRENTS, VOLTAGES OR MAGNETIC FIELD
HOW DOES DIMENSIONAL SCALING AFFECT OUTPUT?
DOES SCALING IMPROVE OPERATING TEMPERATURE?
HOW LARGE ARE THE CURRENTS, VOLTAGES, ETC. AND IS DISSIPATION
AND HEATING CRITICAL?
WHAT ARE THE BEST MATERIALS?
WHAT ARE THE BEST CIRCUIT ARCHITECTURES?
CAN THEY BE MANUFACTURED COST EFFECTIVELY?
IS IT WORTH THE EFFORT???
FUTURE APPLICATIONS
(MY VISION)
“INTELLIGENT” SENSORS
NONVOLATILE-REPROGRAMMABLE COMPUTER
>REPLACE: FPGA and ASIC
>INSTANT ON COMPUTER
MOBILE COMPUTING AND COMMUNICATIONS
BIO-MEDICAL IMPLANTS
>MONITORING OF PATIENT FUNCTIONS
>NEURAL PROSTHESES
>ARTIFICIAL RETINA
AUTONOMOUS “SMALL” ROBOTS
HIGH SPEED DIGITAL SIGNAL PROCESSING (FASTER & COOLER)
SUPERCOMPUTING
MULTIFUNCTIONAL SYSTEMS
NANOELECTRONIC AND NANOMAGNETIC DEVICES
RESONANT TUNNELING DIODES (RTD)
NANOWIRE TRANSISTORS (NW)
MAGNETOELECTRONIC DEVICES
NANOMAGNETIC DEVICES
SPINTRONIC DEVICES
SINGLE ELECTRON TRANSISTORS (SET)
QUANTUM DOTS (QD)
CARBON NANOTUBE TRANSISTOR (CNT)
MOLECULAR SWITCHES AND TRANSISTORS
QUANTUM COHERENCE DEVICES
PROPERTIES OF INTEREST
ULTRA LOW POWER DISSIPATION
BATTERY LIFE
HIGH DENSITY CIRCUITS
COOLER CIRCUITS
HIGH SPEED
DEVICE SWITCHING
CIRCUIT ARCHITECTURES-PARALLEL COMPUTING
CIRCUIT COMPACTNESS
3 DIMENSIONAL INTEGRATION
MULTIFUNCTIONALITY
NONVOLATILITY
SEMICONDUCTOR NANOWIRES
WHY?
LOW CURRENTS
ALL SEMICONDUCTORS AND MANY OTHER MATERIALS
DIFFERENT HETEROJUNCTION DEVICES
GROW ON ANY SUBSTRATE
PERFECT INTERFACES (LESS SCATTERING AND OTHER LOSS)
SIZE CONTROL (> 10 NANOMETERS)
ISSUES?
DEVELOP NEW TECHNOLOGY
CIRCUIT DESIGNS AND NEW ARCHITECTURES
MATERIALS FLUCTUATION (IMPURITIES)
RESONANT TUNNELING DIODE
WHY RESONANT TUNNELING DIODES?
INTRINSIC SWITCHING SPEED IS OVER 3 TERAHERTZ
NONLINEAR I-V CHARACTERISTIC
FEWER DEVICES IN CIRCUIT IMPLEMENTATIONS (THAN CMOS)
LOW POWER DISSIPATION
VERSATILE FUNCTIONALITY-PERFORMS ALL DSP FUNCTIONS
PROVEN WAFER SCALE FABRICATION
TEMPERATURE INSENSITIVE
HIGH SPEED DSP CIRCUITS-50 GHZ
HYBRID DEVICE-RTD / HEMT (InGaAs/InP)
50 FEMTOSECOND PHASE NOISE CLOCKS
POSSIBILITY OF THREE TERMINAL DEVICE
PHOTOSENSITIVE RESPONSE
100 Nanometer
Diameter
First implementation of a 1D heterostructure nanoelectronic device in a nanowire
as a double-barrier resonant tunneling diode (DBRTD) in InAs with InP barriers.
3 TERMINAL RTD
PERMEABLE BASE-RTD
SINGLE ELECTRON TRANSISTORS
WHY?
VERY LOW POWER
HIGH DENSITY CIRCUITS
MEMORY CIRCUITS DEMONSTRATED
ISSUES:
OPERATING TEMPERATURE
CONTROL OF DIMENSIONS AND MATERIALS
ELIMINATION OF SPURIOUS CHARGES
PROBLEMS
COMPLEXITY OF INTERCONNECTS
CLOCKING OF SIGNALS ACROSS THE CIRCUITS
DEVICE TO DEVICE VARIATIONS
TEMPERATURE OF OPERATION
CNN-UNIVERSAL MACHINE
IMAGE PROCESSING COMPUTER
PROGRAMMABLE IMAGE PROCESSING COMPUTER ON A CHIP
2 D ARRAY OF PROCESSING ELEMENTS
HIGH LEVEL PROGRAMMING LANGUAGE
ON-CHIP A/D AND D/A
IMAGE FUSION
CURRENT PROJECTS:
MULTI-LEVEL CNNs
INTEGRATION OF FOCAL PLANE ARRAYS ON CNN CHIP
EXPLORING NEW APPLICATIONS & ALGORITHMS
TACTILE SENSING
FACIAL RECOGNITION
AUTONOMOUS ROBOTS
REAL-TIME IMAGE PROCESSING FOR MEDICAL IMAGING,
COLLISION AVOIDANCE, OTHERS
Template configurations I: Spatial
feedback
xij - state/ yij - output
X2 (self)
x2
x2
x2
z- bias (space invariant)
zij - bias
uij - input
a 11 a 10 a 11 
A   a01 a00 a01 ,
 a11 a10 a11 
0 0 0
B  0 b00 0,
0 0 0
z1  i0 , z ij  iij .
Comparison of different CNNUM solutions
Clock
frequency
Feature size
chip area [cm2]
number of
physical
processing
element
Cascadability
Dissipation
3*3
convolution
Erosion/
Dilation
Laplace
(15 iterations)
Pentium
IV
Intel
Itanium
TMS
320C6
X
VIRTEX
XCV300
VIRTEX
XCV6000
CASTLE
With
pipeline
64*64
CNN-UM
128*128
CNN-UM
IBM 10
TeraOps
2GHz
1.5 GHz
1.2GHz
200MHz
200MHz
1/10MHz
32MHz
700MHz
0.13 µm
1.27
1
0.13 µm
3.74
1
0.12 µm
1.1
1
0.22 µm
1.2
< 12
(2bits)
200/400
MHz
0.15 µm
3.5
< 12 (2bits)
0.35 µm
0.68
3*2
0.5 µm
1
4096
0.35 µm
1.45
16384
0.18 µm
6.9468 m2
65536
no
50 W
no
130 W
no
1W
yes
1.8 W
yes
3W
yes
< 0.8 W
yes
1.3 W
yes
<4W
140
110
16.384
41 (6 bit)
20 (6 bit)
10.6
1.749
270
220
32.768
82 (6bit)
41 (6bit)
10.6
1.749
3.18
2000
1560
245.7
615
307
2.67 (12 bit)
1.34 (6 bit)
5.34 (12 bit)
2.67 (6 bit)
39.6 (12 bit)
19.8 (6 bit)
no
491.520
kW
3.18
11.5
1.8975
3.45
Picture size: 128pixel*128 pixel
Running times in microsec
RTD BASED CNN
UTILIZE THE NONLINEAR CHARACTERISTIC OF RTD
USE RTD AS SOURCE CONTACT OF HEMT
CIRCUIT MODELING USING Q-SPICE
NANOMAGNETICS
LOW POWER-NONVOLATILE ELECTRONICS
INTEGRATION OF HIGH DENSITY MEMORY WITH CPU
REPROGRAMMABLE LOGIC
MAGNETIC LOGIC ELEMENTS
SINGLE DOMAINS IN MAGNETIC NANOWIRES
HIGH DENSITY MEMORY
Hybrid Hall Effect Device
AFM of f = 500 nm
prototype
Ferromagnetic
element (nonvolatile states)
V+
I+ V negative
bistable ferromagnetic film
V-
nonconductive
region; radiation
damage by FIB
Mark Johnson, NRL
Physical
principle
I-
Materials: III-V’s
(e.g. InAs, GaAs)
and SOI
Output: 30 mV (typ.)
Write: pulsed I in write
wire
Read: fringe-field Hall
effect
Iw
Integrated
operation
I-
I+
Write
B wire
TOP VIEW
A
C
Bilayer F film; 2 bits / cell,
NDRO
• 2 F
elements
stacked
• Each with a
different
moment,
switching field
60 nm FeCo
75 nm Py
90 nm SiO2
Write: 2 unique values of switching field
Read: 4 discrete output values
8
RH (Ohms)
6
4
2
0
-200
0
H (Oe)
200
Nonvolatile Gates: New paradigms for
Reprogrammable Logic
• Begin with existing, inflexible Field Programmable Gate Array (FPGA)
architecture
– Use Nonvolatile HHE devices for Look Up Tables (LUT) in each
cell and for switches that interconnect cells
– Result is highly flexible Reprogrammable Gate Arrays
• Dynamically Reprogrammable Boolean Gates
– Use 3 input terminals - A, B and Control (C) - and 2 clock cycles
– Control pulse dynamically determines one of the four basic
Boolean operations: AND, OR, NAND or NOR
– Result is latched for next, asynchronous logic step
– Control pulse is part of data stream: Permits remote programming
• HHE Nonvolatile gates are also memory cells
– Integration of logic and memory is automatically achieved
– Chip sectors can be continuously apportioned to memory or logic
– Chip can be continuously (and remotely) reprogrammed for new
functions
MRAM
>BASED ON GIANT MAGNETORESISTANCE EFFECT IN MULTILAYER
METAL FILMS
>USE OF TUNNELING MAGNETORESISTANCE FOR LARGER EFFECTS
>INTEGRATED NON-VOLATILE SRAM
>STAND ALONE HIGH DENSITY MEMORY
FET is used for read-addressing.
One FET per bit is required.
Vertical GMR Memory Design:
A memory cell
1.0
Normalized GMR
hard magnetic
layers
soft magnetic
layers
0.5
0.0
-0.5
-1.0
-60
-40
-20
0
20
40
Sense Current (mA)
M
M
bit line
Nanomagnetic memory: Performance improves as magnetic
element shrinks in size
60
Vertical GMR Memory (VMRAM)
Jimmy Zhu, Carnegie Mellon University
A memory cell
paired word lines
bit line
bit line
Ring shaped vertical
GMR memory stack
Magnetic Switching Speed
read:
2x0.4
ns
1.0
I
I
Ibit
Normalized GMR Output
paired word lines
0.5
0.0
write:
0.8ns
-0.5
-1.0
I
I
One possible chip layout
0.0
0.2
0.4
0.6
0.8
1.0
Time (ns)
1.2
1.4
1.6
Energy Density ( erg/cm3)
Ultimate Density
4x10
6
3x10
6
D=1/(4l2)
C ir c u la r M a g n e tiz a tio n
L in e a r M a g n e tiz a tio n
dc = 10 nm
2x10
6
1x10
6
M
0
5
10
15
20
25
30
Inner Diameter d (nm)
Ultimate density 400
Gbits/in2 or 63 Gbits/cm2
M
NiFeCo 15Å
SPIN MOMENTUM TRANSFER
N
F1
N
F2
N
N
F1
N
F2
N
N = normal metal layer
F1 = fixed ferromagnetic layer – spin polarizer
F2 = “free” ferromagnetic layer – excitable nanomagnet
V+
Au
I+
~40 nm
Insulator
Free
Fixed
VNanopillar device
Katine et al. (Cornell)
Cu
Nanocontact device
Rippard et al. (NIST)
I-
Advantages of Spin-Current-Switched MRAM Over
Field-Switched MRAM
magnetic-field switching
potential spin-transfer switching
• Spin
transfer gives stronger torques per unit current than for magnetic fields,
in devices smaller than about 250 nm.
• Improved write margin: short-range forces.
• Improved density and reduced process adder (1-2 masks instead of 3-5).
• Excellent scaling to small sizes -- switching currents can be minimized while
maintaining magnetic anisotropy barriers for thermal stability
Requirements for an effective spin switched MRAM Bit:
1 Optimizing to allow smaller currents (0.1-0.2 mA) for switching of stable nanomagnets
2. Higher impedances (~1-10 kΩ) to be compatible with readout by silicon electronics.
3 Manufacturable – process margins.
Dense, fast, non-volatile memory – low power and high performance embedded
Alternative Spin Transfer Device
Reversible Domain Wall Displacement
Domain wall drag
D.W.

M
L. Berger, B Amer. Phys. Soc. 17 571 (1972)
At sufficiently high bias currents domain
wall will be dragged by the current
M
Freitas & Berger , J Appl Phys 57 1266 (1985)
Electron Flow
SEM and MFM (b) of domain wall
device. Domain wall is trapped in
the left constriction
Low Ic
Grollier et al. APL 83 509 (2003)
Tsoi et al. APL 83 2617 (2003)
Speed? Scalability?
Thermal stability for high density memory?
Quantum-Dot Cellular
Automata
A Quantum-Dot Cell
Represent
2 extra electrons
binary
information by
charge
An Array of Cells
configuration
Neighboring
cells tend to
A cell with 4 dots
align due to direct
Coulombic coupling
Magnetic QCA
Magnetic nanopillar as bistable switch:
Due to shape anisotropy there is a typically
few hundred room-temperature kT energy barrier
between the two stationary states.
Assigning logic values:
‘0’
‘1’
QCA – idea: ground state depends
on the state of the neighbors:
Different geometry
logic operations
different
University of Notre Dame
Ground state
Metastable state
Center for Nano Science and Technology
The Nanomagnet Wire and Inverter
Magnetic Force Microscopy Image:
Micromagnetic Simulation of a six-dot chain
1.5μm
Physical basis:
Antiferromagnetic coupling
between single–domain dots
Logic equivalent
Adiabatic Switching of the Nanowire
H ext
0.5μm
Input dot: retains its magnetization
t
Clocked Operation
Output block
Input block
CMOS preprocessor circuits
Input realization
CMOS postprocessor circuits
Integrated Nanomagnet Logic
Output realization
Information flow
Concept of edge-driven computing:
Only dots on the edge of the structure
are accessed individually
Magnetic QCA
− a system built on majority logic
Input 1
Input 3
Input 2
Output
‘Central dot’
Input 1
Input 2
Input 3
Output
1
0
0
0
1
0
1
1
1
1
0
1
1
1
1
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
1


Input 2
OR
Input 3
Input 2
AND
Input 3
POSSIBLE NANODEVICE ARCHITECTURES
EDGE DRIVEN COMPUTERS
PIP-PROPAGATED INSTRUCTION PROCESSOR
QCA-QUANTUM CELLULAR AUTOMATA
MQCA-MAGNETIC QUANTUM CELLULAR AUTOMATA
CNN-CELLULAR NONLINEAR NETWORK
FIELD REPROGRAMMABLE GATE ARRAY
MULTIVALUE LOGIC/MULTIVALUE MEMORY
3 DIMENSIONAL MULTIFUNCTIONAL PROCESSORS
PARALLEL COMPUTING
END
Semiconductor Spintronics
Resonant Interband Tunneling Diode
AlSb
Ferromagnetic
Semiconductor
p - GaMnSb
AlSb
GaMnSb
Ef
InAs
InAs
Ec
Electrons tunnel
through
SPIN-POLARIZED
valence band states
of quantum well
Ev
• bias dependent spin-polarized source
• gated RITD (with polarized emitter)
Jonker
RTD / GMR Hybrid Devices
exchange
coupled
GMR
resistor
RTD
H input
60
30
RITD
20 um
3.4
HIGH
LOW
30
20
10 um
Resistance ( )
40
 - sat / sat = 28 %
25
3.2
20
15
3
10
2.8
10
5
0
2.6
0
0.1
0.2
0.3
0.4
0.5
Voltage (V)
0.6
0.7
R/R (%)
Current (mA)
50
Ho = 80 Oe
0.8
0
-1
-0.5
0
0.5
dR/R=
28%
1
Applied Field (kOe)
T = 300 K
May 2000
RTD - GMR Hybrid
MOnostable-BIstable Logic Element – MOBILE
Maezawa & Mizutani (1993)
MOBILE INVERTER
RTD-FET Logic Cell
Chen et al, IEEE Elec. DeviceLett. 16, 70 (1995)
Bias Voltage (Clock)
RTD - Large
Input
Voltage
FET
Bias
Output
RTD - Small
Input
Output
Fast, low component count cell
for logic, digital signal processing
High (1)
0V
Low (0)
Jonker
Device opportunity: spintronic currents without injection
Bias
M
Write
Read
Fabricated prototype device structure integrating
electronics, magnetics, and photonics…
SPINTRONICS
ELECTRON SPIN CONTROLLED ELECTRONICS
ULTRA-LOW POWER
MULTIFUNCTIONAL DEVICES
HIGH SPEED
ISSUES:
MATERIALS (LOW OPERATING TEMPERATURE)
MOBILITY
NEED ELECTRON INJECTION
(May be useful for optical applications, I.e. THz switching and modulation)
(Electron spin control for quantum information processing)
MATERIALS-BEYOND SILICON CMOS
III-V COMPOUND SEMICONDUCTORS
HETEROJUNCITONS
NANOWIRES
FERROMAGNETIC METALS
MAGNETOELECTRONICS
MAGNETIC NANOWIRES-SINGLE DOMAINS
MAGNETIC SEMICONDUCTORS
SPINTRONICS
SILICON/GERMANIUM
CARBON NANOTUBES
MOLECULAR SWITCHES
Reprogrammable Logic: FRePGA
• Need: nonvolatile switch, ME + FET
• Then: FRePGA chip uses ME for LUT and
interconnect switches
• Programming of FRePGA is by software - NO
ROM needed
• ME is nonvolatile; values for LUT and
interconnect switches are always there: Instant
ON
• Flexibility: Reprogrammable
ME LUT
– Hardware upgrade is by software
– Reprogram blocks at any time by storing
new values in ME LUT
– Blocks can also be apportioned for use as
nonvolatile RAM, as needed
• ME cell size < SRAM so Block Density
increases by 2x
Xylink, Infineon