Download Slajd 1 - MOS-AK

Characterization of FD-SOI MOSFETs
Based on EKV model
Daniel Tomaszewski1, Denis Flandre2, Piotr Grabiec1,
Andrzej Kociubinski1, Christian Renaux2, Krzysztof Kucharski1
1 Institute of Electron Technology, Warszawa, Poland
2 Université Catholique de Louvain, Louvain-la-Neuve, Belgium
presented by Daniel Tomaszewski
MOS-AK Workshop, Grenoble, 2005
OUTLINE
 MOTIVATION
 MOSTXX APPLICATION
 EKV MODEL IMPLEMENTATION
 EXTRACTION OF THE PARAMETERS
 SUMMARY, FUTURE
MOTIVATION
The FD-SOI becomes an attractive choice for small
research groups and SME’s, where research projects
related to ASICs /MEMS integration are carried out.
A MOSTXX application for MOSFET parameter
extraction has been developed in the ITE as a cost
effective tool for characterization of the CMOS ICs.
Recently the EKV model, has been implemented.
The paper reports results of EKV model parameter
extraction for the FD-SOI MOSFETs. The analysis has
been done using the MOSTXX software.
MOSTXX application
• Integration with MS Excel
• „Local” extraction:
• Threshold voltage
cs-05/1/(9.2;55.2)/e21_50x50; mob.mod. 2,3
9.0E-2
Mobility [m^2/Vs]
1E+5
7.0E-2
• „Global” extraction:
6.0E-2
5.0E-2
LEV=3
4.0E-2
• MOSFETs parameters
3.0E-2
2.0E-2
1.0E-2
0.0E+0
1.6
IFA [A/m^2], IFP [A/m]
• Mobility
LEV=2
8.0E-2
2.1
2.6
3.1
3.6
4.1
4.6
VGS [V]
Area component
1E+2
1E-1
1E-4
Edge component
1E-7
1E-10
0.1
0.2
0.3
0.4
0.5
VF [V]
0.6
0.7
0.8
• Diodes parameters (I-V,
C-V)
• Extraction of dimensions
variations using sets of
devices
EKV MODEL IMPLEMENTATION
The EKV model accounts for weak
and strong inversion ranges and is
based on interpolation of F(v)
The Oguey, Cserveny approximation
 ev
for v  0

F( v)    v 2
   for v  0
 2
 
F( v)  ln 1  ev
The approximation in the EKV enhanced in order to
calculate F”(v)
2

2
TECHNOLOGY
0.75÷2 µm FD-SOI CMOS process
on SmartCut UNIBOND wafers.
Semi-recessed LOCOS used to isolate
the devices.
n+-poly-Si gate material
Boron implantation of the n- and p-channel MOSFETs
Basic parameters of the process:
Buried oxide thickness
Final thickness of the silicon film
Gate oxide thickness
Junction depth
TBOX = 400 nm
TSi = 80 nm
TOX = 31 nm
XJ = TSi(assumed)
DEVICES
UCL0410_A1_std_Pi_w3_l3 / 1
1.0E-3
1.0E-3
1.0E-5
1.0E-5
1.0E-7
1.0E-7
IS [Amps]
ID [Amps]
UCL0410_A1_std_Ni_w3_l3 / 1
1.0E-9
Vback= -1.5; lin
1.0E-11
1.0E-9
Vback= -1.5
1.0E-11
Vback= -1.5; sat
Vback= -1.5
Vback= 0; lin
Vback= 0
Vback= 0; sat
1.0E-13
Vback= 0
1.0E-13
Vback= 1.5; lin
Vback= 1.5
Vback= 1.5; sat
Vback= 1.5
1.0E-15
1.0E-15
-2
-1
0
VG [Volts]
1
2
3
-3
-2
-1
VG [Volts]
0
1
2
I(VGS) data of intrinsic (I-type) n- and p-channel MOSFETs
UCL0410_A1_std_Pp12_w3_l3 / 1
1.0E-3
1.0E-3
1.0E-5
1.0E-5
1.0E-7
1.0E-7
IS [Amps]
ID [Amps]
UCL0410_A1_std_Np12_w3_l3 / 1
1.0E-9
Vback= -1.5
1.0E-11
1.0E-9
Vback= -1.5
1.0E-11
Vback= -1.5
Vback= -1.5
Vback= 0
Vback= 0
Vback= 0
1.0E-13
Vback= 0
1.0E-13
Vback= 1.5
Vback= 1.5
Vback= 1.5
Vback= 1.5
1.0E-15
1.0E-15
-2
-1
0
VG [Volts]
1
2
3
-3
-2
-1
VG [Volts]
0
1
2
I(VGS) data of highly doped (P12-type) n- and p-channel
MOSFETs
DEVICES
UCL0410_A1_std_Np2_w3_l3 / 1
4.0E-5
UCL0410_A1_std_Np12_w3_l3 / 1
2.0E-5
MESURE MOS_Id_Vd
Vback= 0
3.5E-5
1.6E-5
3.0E-5
1.4E-5
2.5E-5
ID [Amps]
ID [Amps]
MESURE MOS_Id_Vd
Vback= 0
1.8E-5
2.0E-5
1.5E-5
1.2E-5
1.0E-5
8.0E-6
6.0E-6
1.0E-5
4.0E-6
5.0E-6
2.0E-6
0.0E+0
0.0E+0
0
0.5
1
1.5
VD [Volts]
2
2.5
3
0
0.5
1
1.5
2
2.5
3
VD [Volts]
I(VDS) data of P2- and P12-type n-channel MOSFETs;
cumulative boron implantation gives so high boron
concentration in the Si film, that “kink-effect” appears
EXTRACTION OF PARAMETERS
UCL0410/A1/1/Np1_w3_l3; VBS=0 V; VGS=.3,.6,.9,1.2,1.5 V
UCL0410/A1/1/Ni_w3_l3; VBS=0 V; VGS=.3,.6,.9,1.2,1.5 V
6.0E-5
1.0E-4
5.0E-5
EKV
EKV
4.0E-5
ID [A]
ID [A]
8.0E-5
3.0E-5
6.0E-5
4.0E-5
2.0E-5
2.0E-5
1.0E-5
0.0E+0
0.0E+0
0
0.5
1
1.5
2
2.5
3
0
0.5
1
VDS [V]
UCL0410/A1/1/Np12_w3_l3; VBS=0 V; VGS=.3,.6,.9,1.2,1.5 V
2
2.5
3
n-channel MOSFETs
Parameter
1.4E-5
Unit
I
P1
P2
P12
VTO
V
-0.254
0.364
0.640
1.095
GAM
V0.5
0.200
0.500
0.700
1.000
8.0E-6
PHI
V
0.200
0.500
0.720
0.800
6.0E-6
KP
A/V2
1.210E-4
8.845E-5
6.122E-5
5.785E-5
4.0E-6
UCRIT
V/m
1.000E+6
1.000E+6
3.000E+6
5.000E+6
2.0E-6
LAMBDA
-
0.968
1.983
1.000
0.429
0.0E+0
LETA
-
1.917
2.705
4.054
3.142
NUO
-
1.106
0.863
0.932
0.884
1.2E-5
1.0E-5
ID [A]
1.5
VDS [V]
EKV
0
0.5
1
VDS [V]
1.5
2
SUMMARY
The EKV model implemented in optimization tool may be
useful for characterization of FD-SOI MOS transistors.
The results of extraction of FD SOI MOSFETs parameters:
• GAM, PHI parameters estimated “manually” because of
too small number of back gate bias voltages.
• VTO, KP, UCRIT, LAMBDA related to boron concentration
• NUO is below 1, except of I-type device
Square-root VT(VB) dependence should be revised
P-channel MOSFETs devices will be characterized
Thanks a lot
for your attention
Acknowledgement
The authors would like to express thanks to
Dr Władysław Grabiński from Geneva Modeling Center,
Freescale for encouragement towards this work and
helpful discussions during its preparation.
http://www.ite.waw.pl
[email protected]