Download ASIC 120: Digital Systems and Standard

ASIC 120: Digital Systems and
Standard-Cell ASIC Design
Tutorial 1: Introduction to Digital
Circuits
January 25, 2006
1
Outline
• Digital Systems
• Digital Design and its relation to ASICs
• Combinational Logic
– NOT, AND, OR, XOR, NAND, etc.
– mux, half-adder, full-adder
• Sequential Logic
– flip-flop/register, shift register, counter
2
Digital Systems
• Analog vs. Digital
– continuously varying vs. discrete
– imprecise vs. precise
– 0..1 vs. 0 or 1
• Digital systems excel at…
– repetitive calculations
– large amounts of data
– reproducible results
3
Digital Systems
• Implemented in integrated circuits (ICs)
mounted on a printed circuit board (PCB)
4
The Big Picture
5
The Big Picture
Freescale
PowerPC
microprocessor
(PPC)
MPC850 family
RAM
Xilinx
Spartan-II
XC2S30
FPGA
Altera
PLD
Ethernet Connector
6
Components of a Digital System
• Printed circuit board (PCB)
• Embedded software
– microprocessor
– microcontroller
– digital signal processor (DSP)
• ASIC
• Programmable Logic Device (PLD)
– FPGA, etc.
7
ASICs
• Application Specific Integrated Circuit
– from a user perspective, implies integrated circuit with
a specific application
– from a design perspective, implies any integrated
circuit
• Since we are designers, ASICs include
–
–
–
–
–
–
SRAMs
phase locked loops (PLLs)
microprocessors
analog-to-digital converters
FPGAs
etc.
8
Consider an ASIC
• Physically comprised of
– Package
– Pins
– Silicon wafer
•
•
•
•
metal interconnect layers
insulating layers
vias
at the bottom, transistors resting on a silicon
substrate
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Consider an ASIC: Package
10
Consider an ASIC: Side View
Source: Figure 3-11 from ECE 438 textbook (Rabaey, Jan M., Anantha Chandrakasan,
Borivoje Nikolić, “Digital Integrated Circuits: A Design Perspective,” 2nd Edition;
Pearson Education: New Jersey, 2003.)
11
Consider an ASIC: Substrate
Source: Figure 3-13 from ECE 438 textbook (Rabaey et al., “Digital Integrated
Circuits,” 2nd Edition)
12
Consider an ASIC
• Conceptually
– System
– Module
– Gate
– Circuit
– Device
Source: Figure 1-6 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,”13
2nd Edition)
FPGAs
• Field Programmable Gate Array
– part of the Complex Programmable Logic
Device (CPLD) family of PLDs
– essentially reprogrammable hardware
• FPGAs can be very small or very big
– clock rates over 1 GHz
– implement multiple 32-bit processors
14
Components of an FPGA
•
•
•
•
Logic Elements (LEs)
Routing
Input/Output logic
Extra features
– clocking
– memory
– memory interfaces
– multipliers
15
The Logic Element
• Two main parts
– Look-Up Table (LUT)
for combinational logic
– Flip Flop (FF) for
sequential logic
(memory)
Lookup
Table
Flip-Flop
Clock
16
Top Level View of an FPGA
17
Top Level View of an FPGA
18
Digital ASIC/FPGA Design Flow
•
•
Dependent on target environment,
process, resources available, etc.
Generic flow:
1. System architecture
2. Register Transfer Level (RTL)
•
•
high level, synthesizable, optimized
functional simulation, timing simulation
3. Synthesis
•
more simulation
4. Manufacturing
•
testing
19
Register Transfer Level (RTL)
• This is where we start
– schematic
– hardware description languages (VHDL, etc.)
20
Combinational and Sequential
Logic
• We can break a
digital system into two
types of logic
• Combinational
Input
In
Out
Output
Combinational
– computation happens
in a linear fashion
Feedback
• Sequential
– computation involves a
feedback loop
(memory)
Input
In
Out
Output
Combinational
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RTL and Combinational/Sequential
Logic
Sequential
Feedback
Data
Out
Data
In
Register
Cloud
of Logic
Register
Cloud
of Logic
Register
Clock
Combinational
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Combinational Logic: NOT
Truth Table
Input
A
Output
X
0
1
1
0
Boolean algebra expression: X = A
23
Combinational Logic: AND
A
B
X
0
0
0
0
1
1
0
0
0
1
1
1
Boolean algebra expressions: X = A  B
X = AB
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Combinational Logic: OR
A
B
X
0
0
0
0
1
1
0
1
1
1
1
1
Boolean algebra expression:
X=A+B
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Combinational Logic: XOR
A
B
X
0
0
0
0
1
1
0
1
1
1
1
0
Boolean algebra expression:
X=AB
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Combinational Logic: NAND
A
B
X
0
0
1
0
1
1
0
1
1
1
1
0
Boolean algebra expressions: X = A  B
X = AB
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NAND: Transistor Schematic
28
NAND: Transistor Layout
vdd
gnd
29
Combinational Logic: NOR, XNOR
A
0
B
0
X
1
0
1
1
1
0
1
0
0
0
A
0
0
B
0
1
X
1
0
1
1
0
1
0
1
X=A+B
X=AB
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Building Combinational Circuits
A
B
C
X
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
X = AC + BC
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Combinational Logic: MUX
(multiplexer)
A
B
C
X
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
1
1
1
1
0
1
0
1
X = AC + BC
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Half Adder
A
B
S
C
0
0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
S=AB
C = AB
33
Full Adder
S = A  B  Ci
Co = AB + Ci(A  B)
34
Full Adder
35
Full Adder Application: 8-Bit
Ripple-Carry Adder
• Constructed by connecting 8 full adders
together
A0 B0
A
0
B
Ci
Co
A1 B1
A
B
Ci
Co
A2 B2
A
B
Ci
Co
A3 B3
A
B
Ci
Co
A4 B4
A
B
Ci
Co
A5 B5
A
B
Ci
Co
A6 B6
A
B
Ci
Co
A7 B7
A
B
Ci
Co
S
S
S
S
S
S
S
S
S0
S1
S2
S3
S4
S5
S6
S7
Carry
Out
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What I’ve Skipped
•
•
•
•
•
Gates with more than two inputs
Karnaugh maps
Quine-McCluskey method
Binary arithmetic, base conversions
Practical digital circuits have more than 0s
and 1s
• Transmission gates, tri-state buffers
37
Sequential Logic
Input
In
Out
Output
Combinational
Feedback
Input
In
Out
Output
Combinational
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Basic Feedback Element: SR Latch
S
R
Q Qnext
0
0
0
0
0
1
0
0
1
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
0
0
1
1
0
0
N/A
N/A
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Basic Feedback Element: SR Latch
• Simplified truth table:
S
R
Q
0
0
hold
1
0
0
1
1 (set)
0 (reset)
1
1
invalid
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Basic Feedback Element: SR Latch
0
0
1
0
(Hold State)
41
Basic Feedback Element: SR Latch
0
1
0
0
0
1
(Hold State)
42
Basic Feedback Element: SR Latch
0
1
0
0
(Hold State)
43
Basic Feedback Element: SR Latch
0
0
1
1
0
0
(Hold State)
44
Basic Feedback Element: SR Latch
0
0
1
1
(Set State)
45
Basic Feedback Element: SR Latch
0
1
0
0
1
1
(Set State)
46
Basic Feedback Element: SR Latch
0
1
0
0
1
0
(Set State)
47
Basic Feedback Element: SR Latch
0
0
0
0
1
0
(Set State)
48
Basic Feedback Element: SR Latch
0
0
1
0
1
0
(Set State)
49
Basic Feedback Element: SR Latch
0
0
1
1
1
0
(Set State)
50
Basic Feedback Element: SR Latch
1
0
1
1
(Invalid State)
51
Basic Feedback Element: SR Latch
1
1
0
0
1
1
(Invalid State)
52
Basic Feedback Element: SR Latch
1
1
0
0
1
0
(Invalid State)
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Basic Feedback Element: SR Latch
1
0
0
0
1
0
(Invalid State)
54
Basic Feedback Element: SR Latch
• Q and Q are supposed to have opposite
(“complementary”) values
– i.e., Q = Q
• In the invalid state (S = 1, R = 1) Q ≠ Q
– should be avoided
55
D Flip-Flop or Register
D
Clk Q Qnext
0
0
0 0
0
1
0
0
1 1
0 0
1
0
0
1
1
0
01
01
01
01
1
0
1
0
1
1
0
0
1
1
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D Flip-Flop or Register
• Clock input controls when data output
takes value of data input
– triggered on either rising or falling edge of
clock
57
Latches vs. Flip-Flops
• Latches
– no clock input
– data output changes in response to data input
– level-sensitive
• Flip-Flops
– has clock input
– data output changes in response to data input
on rising or falling clock edge
– edge-sensitive
58
Synchronous vs. Asynchronous
• Synchronous
– circuit operation governed by a clock
– currently more popular and practical
– flip-flops
• Asynchronous
–
–
–
–
–
circuit operation independent of a clock
potentially faster than synchronous
lower power consumption
difficult to design
latches
59
Sequential Constructs
• Shift registers
• Counters
• State Machines (next tutorial)
60
Shift Register
• Consider a series of D flip-flops (DFFs)
connected in series, as a 4-bit shift
register
Data
In
D
Q
DFF
D
Q
DFF
D
Q
DFF
D
Q
Data
Out
DFF
Clk
61
Shift Register
0
0
D
Data
In
Q
DFF
0
0
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
0
Clk
62
Shift Register
1
0
D
Data
In
Q
DFF
0
0
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
0
Clk
63
Shift Register
1
1
D
Data
In
Q
DFF
0
0
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
 (1)
Clk
64
Shift Register
0
1
D
Data
In
Q
DFF
0
0
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
 (0)
Clk
65
Shift Register
0
0
D
Data
In
Q
DFF
0
1
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
 (1)
Clk
66
Shift Register
0
0
D
Data
In
Q
DFF
1
0
D
Q
DFF
D
Q
DFF
0
D
Q
Data
Out
DFF
 (1)
Clk
67
Shift Register
0
0
D
Data
In
Q
DFF
0
0
D
Q
DFF
D
Q
DFF
1
D
Q
Data
Out
DFF
 (1)
Clk
68
Counters: Ring Counter
• Connect shift register output to input
• Add set and clear functionality to DFFs
D
Q
D
DFF
S
C
Q
D
DFF
S
C
Q
D
DFF
S
C
Q
DFF
S
C
Clk
Init
69
Counters: Ring Counter
0
1
D
Q
D
DFF
S
C
0
0
Q
D
DFF
S
C
Q
0
D
DFF
S
C
Q
DFF
S
C
Clk
1
Init
70
Counters: Ring Counter
0
1
D
Q
D
DFF
S
C
0
0
Q
D
DFF
S
C
Q
0
D
DFF
S
C
Q
DFF
S
C
Clk
0
Init
71
Counters: Ring Counter
0
0
D
Q
D
DFF
S
C
0
1
Q
D
DFF
S
C
Q
0
D
DFF
S
C
Q
DFF
S
C
 (1)
Clk
0
Init
72
Counters: Ring Counter
0
0
D
Q
D
DFF
S
C
1
0
Q
D
DFF
S
C
Q
0
D
DFF
S
C
Q
DFF
S
C
 (1)
Clk
0
Init
73
Counters: Ring Counter
1
0
D
Q
D
DFF
S
C
0
0
Q
D
DFF
S
C
Q
1
D
DFF
S
C
Q
DFF
S
C
 (1)
Clk
0
Init
74
Counters: Ring Counter
•
•
Each DFF output is a digit in a binary number
Sequence was: 1000 (8)
0100 (4)
0010 (2)
0001 (1)
1000 (8)
…
0
1
D
Q
D
DFF
S
C
0
0
Q
D
DFF
S
C
Q
0
D
DFF
S
C
Q
DFF
S
C
 (1)
Clk
0
Init
75
T Flip-Flop
• Clock is the only
input
• Output inverts on
rising edge of the
clock (or “toggle”)
input
76
Counters: Binary Counter
• Implemented using series of T flip-flops
• Counts 0000, 0001, 0010, 0011, etc.
Q
Clk
T
Q
T
Q
T
Q
T
77
Counters: Binary Counter
0
Q
Clk
T
0
0
Q
T
0
Q
T
Q
T
78
Counters: Binary Counter
1
Q
Clk
 (1)
T
0
0
Q
T
0
Q
T
Q
T
79
Counters: Binary Counter
0
Q
Clk
 (1)
T
0
1
Q
T
0
Q
T
Q
T
80
Counters: Binary Counter
1
Q
Clk
 (1)
T
0
1
Q
T
0
Q
T
Q
T
81
Counters: Binary Counter
0
Q
Clk
 (1)
T
1
0
Q
T
0
Q
T
Q
T
82
Counters: Binary Counter
and so on…
1
Q
Clk
 (1)
T
1
0
Q
T
0
Q
T
Q
T
83
State Machines
• Useful abstract constructs for more
complex sequential logic
• More on these next time
84
What I’ve Skipped
• Other flip-flops (RS, JK)
• Many other interesting sequential circuits
(barrel shifters, gray counters, etc.)
85
Hardware Description Languages
(HDLs)
• HDL describes in text a digital circuit
• Examples
– VHDL (we will look at this next time)
– Verilog
– AHDL
– JHDL
86
Hardware Description Languages
(HDLs)
• schematics are useful for…
– drawing high level diagrams
– manually working out simple pieces of logic
• HDLs are useful for…
– describing complex digital systems
• HDLs are not...
– software programming languages (C, Java,
assembly, etc.)
87
Summary
• Digital Systems
• Digital Design and its relation to ASICs
• Combinational Logic
– NOT, AND, OR, XOR, NAND, etc.
– mux, half-adder, full-adder
• Sequential Logic
– flip-flop/register, shift register, counter
88
Next Tutorial
• State machines
• Tutorial 1 in VHDL
• Digital Design Thought Process
– VHDL is not a programming language like C
or Java
– hardware entities represented using text
89
UW ASIC Design Team
• www.asic.uwaterloo.ca
• Reference material
– Bryce Leung’s tutorials (UW ASIC website)
– Michael Goldsmith’s tutorials (UW ASIC
website)
– ECE 223, 427, 438 course notes & textbooks
• My contact info:
Jeff Wentworth, [email protected]
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