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Integrated Receivers
for the SKA
Suzy Jackson (CSIRO ATNF – Macquarie)
Background
• Need for cheap receiver emerged from
Luneburg Lens proposal.
• Project parameters developed in conjunction
with Peter Hall (CSIRO/ISPO), Neil Weste
(CISCO), Arnold van Ardenne (ASTRON) and
Jeffrey Harrison (Macquarie).
• Development conducted as joint
CSIRO/Macquarie PhD project.
• Currently unique international SKA project.
Project Rationale
• Similar receiver requirements identified across
all SKA proposals
– Large N small D – one receiver per element
– Small N Large D – many receivers per antenna (Focal
Plane Array) to meet Field of View requirements.
• Cheap highly integrated receivers thus SKA
enabling technology
• “Generic” prototype useful internationally across
wide range of demonstrators – SKAMP, NTD,
EMBRACE…
CMOS for RF?
Advantages:
• High integration levels
• Low wafer costs
• Low power
• Ability to integrate
digital logic
• Strong industry cost &
performance drivers
(wireless networking,
mobile phones)
Detractors:
• Lossy substrate –
poor quality passives
• Currently lower fT
(higher noise) than
GaAs & InP
• Less mature
technology (modelling
issues)
Noise Considerations
Deriving TN(min) for MOS transistors (Lee 1998):
TN(min) scales with fT. Newer processes promise higher
fT, hence lower noise at given frequency.
CMOS Technology
Trends
400
0.4
350
0.35
Transistor Speed
0.3
Gate Length
Length Trend
250
0.25
Speed Trend
200
0.2
150
0.15
100
0.1
50
0.05
0
1994
1996
1998
2000
2002
Year
2004
2006
0
2008
Gate Length (µm)
Transistor f T (GHz)
300
Implying (Disclaimers
Apply)
300
2GHz TNmin
Minimum Noise Temp (K)
250
10GHz TNmin
10GHz Noise Trend
2GHz Noise Trend
200
150
100
50
0
1994
1996
1998
2000
2002
Year
2004
2006
2008
Project Overview
Design and construct 0.18µm RF-CMOS
Integrated Receiver:
• RF frequency range 500 – 1700 MHz.
• Tsys < 50K (uncooled).
• Instantaneous IF bandwidth 500 MHz.
• ~40dB (6 – 8 bits) dynamic range.
• Complete antenna to bits implementation.
• Ambitious specifications for CMOS technology.
Block Diagram
LNA
PASSIVE
HIGHPASS
RF AMP
PASSIVE
LOWPASS
RF AMP
20dB Gain
50K Noise Temp
-10dBm Comp. Point
500MHz
~3rd Order
2dB Ins. Loss
15dB Gain
200K Noise Temp
0dBm Comp. Point
1700MHz
~3rd Order
3dB Ins. Loss
15dB Gain
400K Noise Temp
5dBm Comp. Point
GILBERT CELL
MIXER
ACTIVE
LOWPASS
VGA
SAMPLER
SERIALISER
50 OHM RF IN
500 - 1700 MHz
0dB Conv. Loss
0dB Comp. Point
800K Noise Temp
250MHz
5th Order Active
0dB Ins. Loss
800K Noise Temp
20-25-30dB Gain
800K Noise Temp
0dBm Comp. Point
512Msps
8 bit
E
O
DATA
8.192 Gbps
O
SAMPLE CLOCK
512 MHz
O
LOCAL OSCILLATOR
3000 - 5800 MHz
Q
D
GILBERT CELL
MIXER
Q
ACTIVE
LOWPASS
VGA
SAMPLER
LO AMP
D
Q
Q
0.18 um RF-CMOS
HIGH DYNAMIC RANGE
INTEGRATED RECEIVER
500-1700 MHz RF Band
512 MHz IF (Direct IQ Conversion)
8 bit Digitiser
50 K Noise Temperature (0.7 dB NF)
E
QUADRATURE LO
LO AMP
E
Some Results So Far
LNA Using active noise cancelling for matching transistor
(Bruccoleri 2004).
Next Steps
• Design & layout mixer, IF amps, IF filter, &
sampler as individual components.
• 1st wafer run end 2004.
• Integrate components.
• 2nd wafer run mid-late 2005.
• Final product 2006.