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Advanced VLSI Design
Unit 04: Combinational and
Sequential Circuits
Outline
 Basic CMOS Circuits
 Combinational Circuits
 Sequential Circuits
Slide 2
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=0
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
s
s
Slide 3
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
Slide 4
Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
p+ diffusion
polysilicon
metal1
pMOS transistor
Slide 5
Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
substrate tap
pMOS transistor
well tap
Slide 6
Complementary CMOS
 Complementary CMOS logic gates
– nMOS pull-down network
– pMOS pull-up network
inputs
– a.k.a. static CMOS
Pull-up OFF
Pull-up ON
Pull-down OFF Z (float)
1
Pull-down ON
X (crowbar)
0
pMOS
pull-up
network
output
nMOS
pull-down
network
Slide 7
Gate Layout
 Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
 Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts
Slide 8
Example: NAND3





Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 VDD rail at top
Metal1 GND rail at bottom
32 l by 40 l
Slide 9
Pseudo-nMOS
 In the old days, nMOS processes had no pMOS
– Instead, use pull-up transistor that is always ON
 In CMOS, use a pMOS that is always ON
– Ratio issue
– Make pMOS about ¼ effective strength of
pulldown network
1.8
1.5
load
P/2
1.2
P = 24
Ids
Vout 0.9
Vout
16/2
Vin
0.6
P = 14
0.3
P=4
0
0
0.3
0.6
0.9
1.2
1.5
1.8
Vin
Slide 10
Dynamic Logic
 Dynamic gates uses a clocked pMOS pullup
 Two modes: precharge and evaluate
2
A

2/3
Y
1
Y
1
A
Static
4/3
Pseudo-nMOS

Precharge
Y
A
1
Dynamic
Evaluate
Precharge
Y
Slide 11
The Foot
 What if pulldown network is ON during precharge?
 Use series evaluation transistor to prevent fight.
precharge transistor

Y


Y
inputs
A
Y
inputs
f
f
foot
footed
unfooted
Slide 12
Monotonicity
 Dynamic gates require monotonically rising inputs
during evaluation

– 0 -> 0
A
– 0 -> 1
– 1 -> 1
violates monotonicity
– But not 1 -> 0
during evaluation
A

Precharge
Evaluate
Precharge
Y
Output should rise but does not
Slide 13
Domino Gates
 Follow dynamic stage with inverting static gate
– Dynamic / static pair is called domino gate
– Produces monotonic outputs

Precharge
Evaluate
Precharge
domino AND
W
W
X
Y
Z
X
A
B
C

Y
Z
dynamic static
NAND inverter

A
B


W
X
H
C
Y
H
Z
=
A
B

X
C
Slide 14
Z
Pass Transistor Circuits
 Use pass transistors like switches to do logic
 Inputs drive diffusion terminals as well as gates
 CMOS + Transmission Gates:
– 2-input multiplexer
– Gates should be restoring
S
S
A
A
S
S
Y
Y
B
B
S
S
Slide 15
Sequencing
 Combinational logic
– output depends on current inputs
 Sequential logic
– output depends on current and previous inputs
– Requires separating previous, current, future
– Called state
– Ex: FSM, pipeline
clk
in
clk
clk
clk
out
CL
Finite State Machine
CL
CL
Pipeline
Slide 16
Sequencing Elements
 Latch: Level sensitive
– a.k.a. transparent latch, D latch
 Flip-flop: edge triggered
– A.k.a. master-slave flip-flop, D flip-flop, D register
clk
Q
D
Flop
D
Latch
clk
Q
clk
D
Q (latch)
Q (flop)
Slide 17
Latch Design
 Buffered output
+ No backdriving

X
D

 Widely used in standard cells
+ Very robust (most important)
- Rather large
- Rather slow
- High clock loading
Q


Slide 18
Sequencing Methods
clk
clk
Flop
clk
Flop
Combinational Logic
tnonoverlap
2
Combinational
Logic
Half-Cycle 1
1
Combinational
Logic
Latch
1
Half-Cycle 1
tpw
p
Combinational Logic
Latch
p
Latch
Pulsed Latches
p
tnonoverlap
Tc/2
2
Latch
2-Phase Transparent Latches
1
Latch
Flip-Flops
 Flip-flops
 2-Phase Latches
 Pulsed Latches
Tc
Slide 19
Clocking Summarized
 Flip-Flops:
– Very easy to use, supported by all tools
 2-Phase Transparent Latches:
– Lots of skew tolerance and time borrowing
 Pulsed Latches:
– Fast, hold time risk
Slide 20