Download Pass-Transistor Logic

Pass-Transistor Logic
Inputs
B
Switch
Out
A
Out
Network
B
B
• N transistors
• No static consumption
NMOS-only switch
C=5V
C=5V
M2
A=5V
A=5V
B
B
Mn
CL
M1
VB does not pull up to 5V, but 5V - VTN
Threshold voltage loss causes
static power consumption
Solution 1: Transmission Gate
C
A
C
A
B
B
C
C
C=5 V
A=5V
B
CL
C=0V
Resistance of Transmission Gate
30000.0
Rn
(W/L)p =(W/L)n =
1.8/1.2
R (Ohm)
20000.0
Rp
10000.0
0.0
0.0
Req
1.0
2.0
3.0
Vout
4.0
5.0
Pass-Transistor Based Multiplexer
S
S
S
S
VDD
S
A
VDD
M2
F
S
M1
B
S
GND
In1
In2
Transmission Gate XOR
B
B
M2
A
A
F
M1
M3/M4
B
B
Delay in Transmission Gate Networks
5
5
V1
In
5
Vi
Vi-1
C
0
5
C
0
Vn-1
Vi+1
C
0
Vn
C
C
0
(a)
Req
Req
V1
In
Req
Vi
C
Vn-1
Vi+1
C
C
Req
C
C
(b)
m
Req
Req
Req
Req
Req
Req
In
C
CC
C
C
(c)
CC
Vn
C
Elmore Delay (Chapter 8)
Vin
R1
C1
1
R2
Ri-1
2
C2
i-1
Ci-1
Ri
i
Ci
RN
N
CN
Assume All internal nodes are precharged to VDD and a step voltage is
applied at the input Vin
N
N =
N
N
i
 Ri  Cj =  C i  R j
i=1 j=i
i=1 j=1
Delay Optimization
Transmission Gate Full Adder
P
VDD
Ci
A
P
A
A
P
B
VDD
Ci
A
P
Ci
S Sum Generation
Ci
P
B
Setup
VDD
A
P
Co Carry Generation
Ci
A
VDD
P
(2) NMOS Only Logic: Level Restoring Transistor
VDD
VDD
Level Restorer
Mr
B
A
Mn
M2
X
Out
M1
• Advantage: Full Swing
• Disadvantage: More Complex, Larger Capacitance
• Other approaches: reduced threshold NMOS
Level Restoring Transistor
3.0
without
without
3.0
with
VB
1.0
-1.00
with
5.0
VX
Vout (V)
5.0
2
t (nsec)
1.0
4
(a) Output node
6 -1.00
2
4
t (nsec)
(b) Intermediate node X
6
Solution 3: Single Transistor Pass Gate with VT=0
VDD
VDD
0V
5V
VDD
0V
Out
5V
WATCH OUT FOR LEAKAGE CURRENTS
Complimentary Pass Transistor Logic
A
A
B
B
Pass-Transistor
F
Network
(a)
A
A
B
B
B
Inverse
Pass-Transistor
Network
B
B
A
F
B
B
A
A
B
F=AB
A
B
F=A+B
F=AB
AND/NAND
A
F=AÝ
(b)
A
A
B
B
F=A+B
B
OR/NOR
A
EXOR/NEXOR
F=AÝ
4 Input NAND in CPL