Download Vratislav Michal

Fixed-gain CMOS Differential Amplifiers
for the
40 K to 390 K Temperature Range
Vratislav MICHAL, Alain J. KREISLER and Annick F. DÉGARDIN
Paris Electrical Engineering Laboratory (LGEP), Gif sur Yvette, France
Supélec; CNRS UMR 8507; UPMC - Univ Paris 06; Univ Paris Sud 11
Geoffroy KLISNICK, Gérard SOU and Michel REDON
Electronics and Electromagnetism Laboratory (L2E), UPMC - Univ Paris 06 ,
4 place Jussieu, Paris, France
Research supported by a Marie Curie Early Stage Research Training Fellowship of the European
Community’s Sixth Framework Programme under contract number MEST-CT-2005-020692
1/ 24
Outline
I. Our objectives
II. Introduction / design approach
III.First design & results
IV.Second design & results
V. Conclusions
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
2/24
I. Our objectives
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
3/24
Goals of the project

Development of wide temperature range CMOS
readout amplifiers for YBaCuO bolometric detectors:


Room temperature semiconducting
Superconducting
Requirements:
77K

40 dB, accurate static gain,

77 K to 300 K temperature range,
OSC

Differential gain BW: DC to several MHz,
FFT

Low noise operation,
DSP ...

High (> 100kΩ) input impedance,

Low power consumption,

Simple architecture.
290K
R(T)
G
R(T)
290K
Low noise Differential CMOS amplifier
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
4/24
II. Introduction / design approach
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
5/24
Four pixel configuration:
differential amplification
IB
G
+
RB4
IB
VB4
+
G
RB3
VB3
+
G
RB2
RBn
G
VBn
VB2
-
+
G
RB1
+
VB1
-
a)
a)
b)
Structure of cascaded amplifier asymmetrical (Rbi is the steady state pixel resistance),
b) Selected differential read-out technique.
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
6/24
II.1 Closed loop differential amplifiers
 Currently, fixed gain amplifiers
are realized as closed-loop
networks with resistor feedback
(differential amplifier,
instrumentation amplifier etc.)
 Thermal noise of resistors can
be dominant!
I+Vcc
B
R2
vn(R1)
U/I
vn(R1)
vb
+in
R1
C
-
Vout
R1
DUT
(pixel)
+
vn(R1)
vn(R2)
A
G2
-in
 Frequency compensation
degrade the GBW and SR
RP
Out
CRM2
CM=C(G2+1)
-Vee
G0=gmRP
G0=gmRPG
 R 
vn ,in  8kTR2 1  2   f
R1 

Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
7/24
II.2 In-structure fixed gain (CMOS)
 + No resistors in the structure 
simplification and silicon surface
save, reduced noise contribution
 + Absence of feedback improves
the time characteristics (no
stability problems), increases the
BW and reduces the power
consumption
IB
eb
en
en
R1
R1
C1
G
DUT
(pixel)
C1
*
 - Linearity, distortion
 - No developed architectures
8kBT
ein 
R1
 2  j  Rb  C1 


j


C

1

* Bolometer noise voltage is neglected
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
8/24
II.3 Open loop amplifiers:
design approach
I1
VDD
I2
M2
+in
+
gm1
IL
-in
Vout
G0 
M1
-
I1
VGS1
vout
g m1

gm2
gm2
KPN W1 L1

KPP W2 L2
+
VSS
(a)
(b)
Gain is given by transistors geometry ratio
Gain is given by ratio of gmx of OTA
For current biased MOS architectures, the transconductance is given by:
g m  2 KP
W
I D SAT
L
The 40dB gain can require the geometric ratio value of transistors up to 10 000×KP/KN!
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
9/24
II.4 Adopted technique
VDD
M1
:
VDD
VBIAS
IM 2
M1
IL
M5
M2
IL
vout
i2
+
MOS diode
transconductance
given by
g m  2 KP
Decreasing the
transconductance by current
sink [PhD F. Voisin, 2005]
W
IL
L
gm'  2 KP 
W1
 IL  IM 2 
L1
Current difference makes the
function very sensitive:
S
gm'
k

1
M2
M1
IL
2
VDD
gm' ( k )
k

k
gm' ( k )

1 k
2 1 k
vL
-
M3
i4
M4
VSS
1 : 1
Proposed method for decreasing
the transconductance by means of
current scaling:
 W4 W1
 L L
W
g m'  2  KPT2   2   4 1
L2  W3 W5
 L L
 3 5
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau


  IL



10/24
III. First design & results
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
11/24
III.1 Design of 1st folded cascode
amplifier in AMS 0.35µm
VDD
IB
M1
vIn+
vInMD2
MC1
V BIAS
M5
V OUT
MD1
ID
ID
MC2
V BIAS
IL
IM
M2
IM
M3
M4
VSS
 DC transfer characteristic:
VOUT  VDD  VTH , P
 W3 W5
L L
2

 3 5
 W2   W4  W1
KPP    
 L2   L4 L1

2
 
 
W
W
1 
   I M 1    4  I B  KPP  D  VGS2  KPP  D  VGS  
 
8 
LD
LD
 
 
 

 Gain is the slope of the DC transfer characteristic:
dVout
G0 
d VGS
VGS  0
IB
1 Leff WD



,
2 Weff LD
2  I L ( VGS 0)
where:
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
Weff
Leff
W2 W4 W1
 
L2 L4 L1

W3 W5

L3 L5
12/24
III.3 Measured DC and AC
characteristics of 1st amplifier
-7
100
10
40
40
-3dB
22
100V/V
11
Measured
" voltage gain (dB) "
Simulated
77K
-60dB/
dec
20
50
20
10-8
10
296K
5.0
0
" input noise (nV/Hz½) "
Vout 33
[V]
00
77K
-1
-1
-0.030
-30
-0.015
-15
0
0.015
15
0.030
30
Vin [mV]
DC transfer characteristic at 290 K
-20
2
100
10
10k4
10
1M6
10
8
100M
1.0-9
10
10
" frequency (Hz) "
AC response and input noise (VDD=5V, IQ=2mA)
 Simple fixed gain architecture: suitable for low noise and large BW operation,
 Gain is fixed by means of geometric ratio: no variation with temperature,
 Linearity is good for small signals,
 DC transfer characteristic  √Vin.
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
13/24
IV. Second design & results
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
14/24
IV.1 2nd amplifier: Linearization
of DC transfer characteristic
VDD
P
Based on cancelling the quadratic terms in the basic
equation of the MOS transistor. The node equation
can be written:
M2
I2
I0
V
I1
1
V
M1
2
N
V  VTH 1  
VDD
P-type
IB
IAUX
In+
ID
I0
TD
I1
I2
ID
IL
V BIAS
T2
2
2
VDD  V  VTH 2

2
 I0
The extraction of output voltage leads
to (assuming β1 = β2, VTH1 = VTH2):
Low g m
composite
transistor
In-
TD
V BIAS
T1
2
V OUT
Low g m
composite
transistor
I0
VDD
V

2
 (VDD  2  VTH )
N-type
IM
IM
IAUX =IM -
IB
2
Linear low gm
CMOS load
Vin =0
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
15/24
IV.2 Analysis of transfer function,
temperature properties
 DC transfer function:
IB
VGS1
IAUX
VGS1
I0
ID2
ID1
Low gm composite
transistors
Vout
TP
TP
I1
P
VBIAS
Vi
Vi=-Vo
I2=I’2
IM1
IAUX =IM -
IB
2


Gain is given by derivation:
I2
Voltage/current
invertot
Vin =0
 We replace the elements without
temperature dependence by C:
G0 T  

Vo
I’2
IM2

2
P
VOUT
-1
IL

W
W
1
1
I B   4  I B  KPP  D  VGS2  KPP  D  VGS 
2
8
LD
LD
1

 VDD 
Weff
2
KPP 
VDD  2  VTH , P
Leff
C
KPP (T )  VDD  2  VTH ,P (T )
G0 
dVout
d VGS

VGS  0
1

2
IB 
KPP 
Weff
Leff
WD
LD

 VDD  2  VTH , P

G
[dB]

 Which leads to:
G0 T 
C

1
T 
KPP (T0 )   
 T0 
x
 VDD  2  VTH , P (T0 ) 1  THX  T  T0   
T[K]
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
16/24
IV.4 DC transfer characteristic
22
" output voltage (V) "
dVout
dVin
11
50
50
50
50
G
G
[dB] [dB]
40
40
40
40
dB
(measured)
30
30
00
30
30
Measured
±2.0V
±2.2V
±2.5V
20
20
-1
-1
20
20
10
10
Simulated
-2
-2
-30
-0.03
-20
-0.02
-10
-0.01
0
10
0.01
20
0.02
10
10
30
0.03
00
0
~0
100
100
" input voltage (mV) "
200
200
300
400
T [K]
DC measured transfer characteristic and
measured voltage gain @ 2.5V, 290 K
Temperature compensated linear amplifier
for three VDD values (2nd amplifier type)
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
17/24
IV.5 Cryogenic tests: DC
Vout
[V]
2
Bleu 290K Vout
[V]
red 77K
Vdd= +/- 2V
1
2
1
0
0
-1
-1
-2
-0.04
-0.02
0
0.02
0.04
Bleu 290K
red 77K
Vdd +/- 2.5V
-2
-0.04
-0.02
0
Vin [V]
0.02
0.04
Vin [V]
DC transfer characteristic for two DC supply values
(2nd type linear amplifier)
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
18/24
V. Conclusions
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
19/24
V.1 Comparison with industrial state
of the art
Key parameters of developed amplifiers
MEASURED PARAMETERS
Operating supply voltage
Quiescent bias current
– 3dB bandwidth @ 290 K
Input noise @ 290 K
Input noise @ 77 K
Gain @ 290K
Δ Gain 270 K ÷ 390 K
Gain error @ 77 K
Tot. harm. distortion @ Vout = 0.3 Vpp
TYPE I AMPLIFIER
4.1 V to 5.5 V
2.1 mA
10 MHz (GBW=1GHz)
5 nV/Hz½
2 nV/Hz½
39.85 dB
– 0.12 dB
– 1.2 dB
1%
Industrial differential amplifiers
TYPE II AMPLIFIER
3.6 V to 5.5 V
1.3 mA
4 MHz @ 5 V
5 nV/Hz½
3 nV/Hz½
39.3 dB @ 5 V
– 0.5 dB @ 4 V
– 1.3 dB @ 4 V
0.03 %
(room temperature)
Type
Configuration
GBW
[MHz]
SR
[µV/s]
VDD
[V]
Iq
[mA]
Input
noise
nV/√Hz
AD8045
LTC6401-20
LT1226
OPA699
OPA2354
INA2331
INA103
OA Bipolar
Fixed gain 20dB+/-0,6dB Bipolar
OA Bipolar
OA Bipolar
OA CMOS
Instrumentation CMOS
Instrumentation BIPOALR
1000
1350
3.3 - 12
19 × 3
3
1300
1000
1000
250
50
80
4500
400
1400
150
5
15
2,85-3,5
5-36
5-12
2,7-5,5
2,5-5,5
9-25
50 × 3
7×3
22,5 × 3
7,5 × 3
0,5
9
2,1
2,6
4,1
6,5
46
1
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
Other
Rin=200Ω
25dB stable
12dB stable
20/24
V.2 Summary

Two amplifiers, based on different techniques of gain setting, have
been designed, fabricated and characterized by measurements in a
wide temperature range.

Both amplifiers exhibit very good performances, competitive with or
superior to the industrial state-of-the-art.

Small size and low consumption make them ideal as versatile blocks
for VLSI integration.

Wide temperature range operation demonstrates robustness of the
design.
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
21/24
V.3 PCB test board with integrated ASIC
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
22/24
Appendix I: Differential (type I) amplifier
designed for 40dB voltage gain
IB
MB3
600.5/8µ
MB2
315/8µ
2360/2µ
vin+
IB/2
MD2
IB/2
500/8µ
M2
100/5µ
vout
vbias
MB6
IM
IM
MB1
Ib=500µA
MC2
501/8µ
MB5
200/8µ
VDD
MO2
15/5µ
100/5µ
MD1
400/8µ
M5
2360/2µ
MC2
501/8µ
38/5µ
M1
vin-
MB4
15/5µ
IL
M3
38/5µ
MO1
M4
15/5µ
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
1000/2µ
VSS
23/24
Appendix II: CMOS AMS 0.35µm
realization of type II amplifier
Schematic view of designed amplifier
Vratislav Michal - Wolte 8, 22-25July 2008, Ilmenau
24/24