Download Modern and Future Processors

Modern and Future
Processors
Dr. Gheith Abandah
5/23/2017
1
History
1946: ENIAC




First Electronic
Computer
100 feet long
18,000 vacuum tubes
Addition takes 0.2 ms
(5 KHz)
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Semiconductor Age
1947: First transistor
1950: BJT
1953: Hearing Aid
Late 1950’s:
Integrated circuits
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Moore’s Law
1965: Intel’s Gordon
Moore predicts that
the number of
transistors on a chip
will double roughly
every year (a decade
later, revised to every
2 years).
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First Microprocessor
1971: Intel 4004
4-bit processor
1/8” by 1/16”
2,300 transistors
10micron PMOS
technology
108 KHz
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More Processors
Processor
Year
Transistors
4004
1971
2,300
8080
1974
4,500
8086
1978
29,000
386
1985
275,000
486
1989
1,200,000
Pentium
1993
3,100,000
Pentium 4
2000
42,000,000
Itanium 2
2003
220,000,000
Dual-Core Itanium 2
2006
1,720,000,000
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Processor Performance
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CINT2000
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Outline
Driving Forces
Technology
 Architectural Innovation

Reasons for the Slowdown
Multi-Core Trend
Future
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Performance Equation
Clock
Processor
Performance = Frequency * IPC
IPC = Instructions Per Cycle
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Driving Forces
Technology & Architectural Innovation
160
Performance
140
120
100
Architecture (52%)
80
Technology (33%)
60
40
20
0
1990
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1992
1994
1996
1998
2000
2002
11
Technology
The IC
manufacturing
technology gives
smaller transistors
every year.
1971: 10 micron
2007: 0.045 micron
→ More transistors
on one chip
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Technology
Smaller transistors →


Cheaper
Switch faster
Gate delays
decrease.
Processors run on
higher frequency.
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Architectural Innovation
Performance = Frequency * IPC
Architects use the extra transistors to
•
•
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execute more instructions per cycle
or increase the frequency.
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Architectural Innovation
Super Pipelining
Superscalar
Dynamic Execution
Multi-Threading
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Executing Instructions
Data
loop: load t1, 0(s1)
load t2, 100(s1)
add t3, t1, t2
store t3, 200(s1)
add s1, s1, 1
bne s1, s0, loop
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Results
Processor
Instructions
Memory
16
Conventional Processor
Instruction 1
Fetch Decode Execute
Write
Instruction 2
Fetch Decode Execute
Write
Frequency = f, IPC = 1/4
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Pipelined Processor
Instruction 1
Instruction 2
Instruction 3
F
D
E
W
F
D
E
W
F
D
E
W
Frequency = f, IPC = 1
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Super-Pipelined
Processor
Instruction 1
Instruction 2
Instruction 3
Frequency = 5f, IPC = 1
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Superscalar Processor
Instruction 1
F
D
E
W
Instruction 2
F
D
E
W
Instruction 3
F
D
E
W
Instruction 4
F
D
E
W
Instruction 5
F
D
E
W
Instruction 6
F
D
E
W
Frequency = f, IPC = 2
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IBM POWER5
Released in 2003: 276 million transistors
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Dynamic Execution
Consider large
instruction window
Execute the ready
instruction
One stalled
instruction doesn’t
necessarily stalls
the entire
processor
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I1I1
I1I1
I1
ALU 1
ALU 2
ALU 3
22
Multi-Threading
The processor executes instructions from
multiple threads.
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IBM POWER5 - Threads
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Intel Micro-architecture
MicroArchitecture
Year
P5
1993
P6
1995
NetBurst
Core
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Processor
Superscalar
Degree
Pipeline
Stages
Pentium
2
5
3
14
2000
Pentium
Pro
Pentium 4
3
20
2006
Core 2 Duo
4
14
25
Outline
Driving Forces
Technology
 Architectural Innovation

Reasons for the Slowdown
Multi-core Trend
Future
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Reasons for the
Slowdown
1. Power = Frequency × Voltage
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× Capacitance
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Reasons for the
Slowdown
2. Processor complexity increases with:
More instructions issued per cycle
 Longer pipeline

3. In most applications, there isn’t enough
instruction level parallelism (ILP) to fill
many pipelines → diminishing returns.
4. Many applications aren’t threaded.
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Reasons for the
Slowdown
We could build a slightly faster chip, but
it would cost twice the die area while
gaining only a 20 percent speed
increase
- Marc Tremblay, Sun Microsystems
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Outline
Driving Forces
Technology
 Architectural Innovation

Reasons for the Slowdown
Multi-Core Trend
Future
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Multi-Core Trend
Modern processor chips contain
processing cores and levels of memory
caches.
manufacturers are building chips with
multiple cooler-running, more energyefficient processing cores instead of one
increasingly powerful core.
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Multi-Core Examples
Company
Intel
IBM
Sun
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Processor
Year
Cores
Core 2 Duo
2006
2
Itanium 2
2006
2
Core 2 Quad
2006
4
Power 4
2001
2
Power 5
2003
2
Cell
2006
9
UltraSPARC T1
2005
8
32
IBM POWER5 Chip
276 million
transistors
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IBM Cell
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IBM Cell Chip
234 million
transistors
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UltraSPARC T1
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AMD Athlon
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Outline
Driving Forces
Technology
 Architectural Innovation

Reasons for the Slowdown
Multi-core Trend
Future
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Future
Research on better semiconductor materials
to build smaller, faster, and cooler transistors.
Fine power management.
Keep tweaking the cores for more
performance optimizations.
Multiple cores are here to stay.
More and larger caches.
Compilers that generate parallel threads
automatically.
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Thank You
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