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Chapter 10 Memories Boonchuay Supmonchai Integrated Design Application Research (IDAR) Laboratory August 7, 2005 B.Supmonchai Outlines Memory Classification ROM, SRAM, DRAM, CAM Memory Architecture Memory Core Circuits Periphery Circuits Reliability Case Studies 2102-545 Digital ICs Memories 2 B.Supmonchai Review: Basic Building Blocks Datapath Execution units Adder, multiplier, divider, shifter, etc. Register file and pipeline registers Multiplexers, decoders Control Finite state machines (PLA, ROM, random logic) Interconnect Switches, arbiters, buses Memory Caches (SRAMs), TLBs, DRAMs, buffers 2102-545 Digital ICs Memories 3 B.Supmonchai A Typical Memory Hierarchy On-Chip Components CPU Board eDRAM Control Cost DTLB RegFile Speed (ns) .1’s Size (bytes) 100’s Instr Data Cache Cache ITLB Datapath Main Board Second Level Cache (SRAM) Main Memory (DRAM) 1’s 10’s 10K’s 100’s M’s K’s highest Secondary Memory (Disk) 1,000’s T’s lowest By taking advantage of the principle of locality: Present the user with as much memory as is available in the cheapest technology. Provide access at the speed offered by the fastest technology. 2102-545 Digital ICs Memories 4 B.Supmonchai Semiconductor Memories Read-Write Memory Random Access SRAM (cache, register file) DRAM Non-Random Access Non-Volatile Read-Write Memory FIFO LIFO Shift Register EPROM E2PROM FLASH CAM Read-Only Memory Maskprogrammed Electricallyprogrammed (PROM) 50% of the transistors in a microprocessor are in the memory (reg file, caches, etc.) 2102-545 Digital ICs Memories 5 B.Supmonchai Memory Timing Definitions Read Cycle Read Read Access Write Cycle Read Access Write Write Setup Write Hold Data Data Valid 2102-545 Digital ICs Memories Data Written 6 B.Supmonchai 1D-Memory Architecture: Decoders M bits S1 N words S2 SN-2 SN-1 S0 Word 0 Word 0 Word 1 Word 2 Storage cell Word 1 A0 A1 A K-1 Decoder S0 M bits Word 2 Word N - 2 Word N - 2 Word N - 1 Word N - 1 Storage cell K = log2N Input-Output (M bits) Too many select signals: N words N select signals 2102-545 Digital ICs Input-Output (M bits) Decoder reduces #s of select signals N words K (= log2N) select signals Memories 7 B.Supmonchai 2D-Memory Architecture: Array-Based AK A K-1 A L-1 Bit line Row decoder 2L-K Storage Cell Word line 1D-architecture suffers from the ASPECT RATIO problem (HEIGHT >> WIDTH) Still too slow for bigger memories (> 256K) because the word and bit lines are too long. M. 2K A0 A K-1 Sense amplifiers / Drivers Amplify swing to rail-to-rail amplitude Column decoder Select appropriate word Input-Output (M bits) 2102-545 Digital ICs Memories 8 B.Supmonchai 3D-Memory Architecture: Hierarchical - Advantages: 2102-545 Digital ICs 1. Shorter word and/or bit lines 2. Block address activates only 1 block saving power Memories 9 B.Supmonchai Data (64 bits) Commands 2102-545 Digital ICs R/W Address (9 bits) Memories CAM Array 29 word x 64 bits Priority Encoder Mask 29 Validity Bits Control Logic Comparand Address Decoder I/O Buffers Contents-Addressable Memory (CAM) 10 B.Supmonchai CAM Operations 3 Modes of CAM Operation: Read, Write, and Match In Match mode, the data are compared to the content in the memories to locate where the data are kept, i.e. its address. The Comparand keeps the data pattern to match and the Mask indicates which bits are significant. All 512 rows of the CAM array then simultaneously compare the significant bits of the comparand with the data contained in that row. Validity bits are set for the rows that contain matched pattern. If there are more than one matched row, the Row address of the CAM array is used to break the tie. “Match Found” bit is set if there is a match. 2102-545 Digital ICs Memories 11 B.Supmonchai Read-Only Memory (ROM) Cells BL BL BL VDD WL WL WL “1” BL WL BL BL WL WL “0” GND Diode ROM No isolation 2102-545 Digital ICs MOS ROM 1 MOS ROM 2 More area and higher drive strength Memories 12 B.Supmonchai MOS OR ROM Implementation BL[0] BL[1] BL[2] BL[3] WL[0] VDD Mirror Cell WL[1] WL[2] VDD Shared to reduce overhead WL[3] Pull-down loads Vbias 2102-545 Digital ICs Memories 13 B.Supmonchai MOS NOR ROM Implementation VDD Pull-up devices WL[0] GND WL [1] WL [2] GND WL [3] BL [0] 2102-545 Digital ICs BL [1] BL [2] Memories BL [3] Missing NMOS means storing a “1” 14 B.Supmonchai MOS NOR ROM Layout BL[0] BL[1] BL[2] BL[3] BL[0] BL[1] BL[2] BL[3] (11l x 7l) WL[0] WL[0] GND (9.5l x 7l) GND WL[1] WL[1] WL[2] GND WL[2] WL[3] GND WL[3] ACTIVE Layer Polysilicon Metal1 2102-545 Digital ICs Diffusion Metal1 on Diffusion Memories CONTACT Layer 15 B.Supmonchai MOS NAND ROM V DD Pull-up devices BL [0] BL [1] BL [2] BL [3] WL [0] No Supply or GND needed in the cell WL [1] WL [2] WL [3] All word lines high by default with exception of selected row 2102-545 Digital ICs Memories 16 B.Supmonchai MOS NAND ROM Layout BL[0] BL[1] BL[2] BL[3] BL[0] BL[1] BL[2] BL[3] (5l x 6l) WL[0] WL[0] WL[1] (8l x 7l) WL[1] WL[2] WL[3] WL[2] Using Implantation WL[3] Drastically reduced cell size but Loss in Performance compared to NOR ROM METAL-1 Layer Polysilicon Diffusion 2102-545 Digital ICs Threshold-Altering Implant Metal1 on Diffusion Memories 17 B.Supmonchai Transient Model for NOR ROM Bit line parasitics (Metal1) Wire resistance (negligible) Wire capacitance Drain capacitance VDD Word line parasitics (polysilicon) Wire resistance Wire capacitance Gate capacitance Metal1 Poly BL rword Cbit WL cword Transient Response time from word line activation to bit line traversing voltage swing (typically 10% of Vdd). 2102-545 Digital ICs Memories 18 B.Supmonchai Transient Model for NAND ROM VDD Word line parasitics (polysilicon) Wire resistance Wire capacitance Gate capacitance BL WL c bit rword cword Bit line parasitics Worst case scenario: when the cascade chain is populated distributed RC model 2102-545 Digital ICs CL r bit Memories (Metal1) Resistance of cascaded transistors dominates Drain/Source and complete gate capacitance 19 Example: 512 512 NOR ROM Word line delay can be computed using the distributed rc-line model where the line consists of M sections/cells. tword B.Supmonchai = 0.38(rword cword)M2 = 0.38(17.5 Ω * (0.049 + 0.75)fF) * 5122 = 1.4 ns Assume a (0.5/0.25) pull-up device and a (1.3125/0.25) pull-down transistor Cbit tbit, HL tbit, LH = 512*(0.8+0.09)fF = 0.46 pF = 0.69(13 kΩ /2 || 31 kΩ /5.25)*0.46 pF = 0.98 ns = 0.69(31 kΩ /5.25)*0.46 pF = 1.87 ns Bit line response time depends on the transition direction. 2102-545 Digital ICs Memories 20 B.Supmonchai Example: 512 512 NAND ROM Using similar technique, word line delay of the NAND ROM can be computed as tword = 0.38(15 Ω * (0.049 + 0.56)fF) * 5122 = 1.3 ns For the bit line, the worst case high-to-low delay occurs when the complete column is populated with 0s except the bottommost transistor. By the distributed rc-line model (which is a fair approximation) tbit, HL = 0.38(8.7 kΩ * 0.85 fF) * 5112 = 0.73 µs Using Elmore delay for the low-to-high worst case delay which occurs when the bottommost transistor is off. tbit, LH 2102-545 Digital ICs = 0.69(31 kΩ /0.0077) * (511*0.85 fF) = 1.2 µs - slow! Memories 21 B.Supmonchai NOR and NAND ROM Disadvantages NOR and NAND ROM inherit all disadvantages of the pseudo-NMOS gate: Ratioed Logic: VOL is determined by the ratio of the pull-up and pull-down devices -> unacceptable transistor ratios. Static Power Consumption: static current exists between the supply rails when the output is low -> severe power dissipation Solution: use fully complimentary NAND and NOR gate (i.e. CMOS) large number of transistor -> large area 2102-545 Digital ICs Memories 22 B.Supmonchai Precharged MOS NOR ROM f VDD pre Precharge devices WL[0] GND WL [1] Can be made as large as necessary, but clock driver becomes harder to design. WL [2] GND WL [3] BL [0] 2102-545 Digital ICs BL [1] BL [2] Memories BL [3] 23 B.Supmonchai Precharged ROM Advantages Eliminates the static power dissipation and the ratioed logic requirements with the same cell complexity. Eliminate the enabling NMOS transistor at the bottom of the pull-down network. Enables independent control of the pull-up and pull-down timing. Almost all of the large memories currently designed, including NVRWM and RAMS, use dynamic precharging. 2102-545 Digital ICs Memories 24 B.Supmonchai Decreasing Word Line Delay Drive the word line from both sides driver WL polysilicon word line driver metal word line Reduce delay by 4 Use a metal bypass polysilicon word line metal bypass WL K cells metal word line Use Silicides 2102-545 Digital ICs Memories 25 B.Supmonchai Decreasing Bit Line Delay (Energy) Reduce the bit line voltage swing (typical value ~ 0.5 V) need sense amp for each column to sense/restore signal Isolate memory cells from the bit lines after sensing (to prevent the cells from changing the bit line voltage further) - pulsed word line generation of word line pulses very critical too short - sense amp operation may fail too long - power efficiency degraded (because bit line swing size depends on duration of the word line pulse) use feedback signal from bit lines Isolate sense amps from bit lines after sensing (to prevent bit lines from having large voltage swings) - bit line isolation 2102-545 Digital ICs Memories 26 B.Supmonchai ROM Perspectives Application-Specific ROMs - custom designed for a particular application Designer has freedom to choose any mask layer (or combination thereof) to program the device. Commodity ROMs - mass-produced memories that later customized according to customer specifications. Mask-programmable: use contact/metal mask to program the memory; becoming unpopular Electrically programmable: use fuses/anti-fuses to program; “write once” (cannot be reprogrammed). 2102-545 Digital ICs Memories 27 B.Supmonchai Non-Volatile Memories (NVM) Basics The Floating-gate Avalanche-injection MOS transistor (FAMOS) Floating gate D Gate Source Drain tox G tox n+ n+_ p Substrate Device cross-section S Schematic symbol Allow threshold voltage to be altered electrically and retained indefinitely. 2102-545 Digital ICs Memories 28 B.Supmonchai Floating-Gate Transistor Programming 5V 20 V VT ~ 7V 10 V S 5V 20 V - 2.5 V S D - 5V S D Programming results in higher V T . 0V Avalanche injection 5V 0V D Removing programming voltage leaves charge trapped 2102-545 Digital ICs Memories 29 B.Supmonchai Note on NVMs NVM structure is identical to the ROM except that it uses FAMOS transistors or similar devices at the cell level instead. The method of erasing is the main differentiating factor between the classes of NVM The programming of the NVM Is typically an order of magnitude slower than the reading operation. Requires high voltage power supply - no less than twice the supply voltage need in the reading operation 2102-545 Digital ICs Memories 30 B.Supmonchai EPROM Summary Based on ROM structure and FAMOS devices. Extremely simple and dense: suitable for large low-cost memories that do not require regular programming. Erased by shining UV lights through a transparent window in the package. UV makes oxide slightly conductive, Q u ic k Tim e ™ a n d a TI FF ( Un c o m p r e s s e d ) d e c o m p r e s s o r a r e n e e d e d t o s e e t h is p ic t u r e . leaking charges very slowly from the floating gate. 2102-545 Digital ICs Memories 31 B.Supmonchai EPROM Drawbacks Erasure process is slow from 10’s to 1000’s sec and must be done “Off System”. Limited Endurance: Number of erase/program cycles is generally limited to at most 1000. Reliability Problems: device threshold might vary with repeated programming. Use on-chip circuitry to control the threshold voltage to within an acceptable range during programming. High power dissipation during programming. 2102-545 Digital ICs Memories 32 B.Supmonchai EEPROM: FLOTOX Device The FLOating-gate Tunneling OXide (FLOTOX) transistor Gate Floating gate I Drain Source 20–30 nm V GD -10 V 10 V n1 n1 Substrate p 10 nm FLOTOX cross section Injecting electrons onto the gate raises VT. Reverse operation (voltage) lower VT 2102-545 Digital ICs Memories Fowler-Nordheim I-V characteristic Bidirectional Programming 33 B.Supmonchai EEPROM Cell Absolute threshold control for FLOTOX transistor is hard. Over-erasing programmed transistor might end up with a depletion device. WL NMOS VDD FLOTOX always ON BL FLOTOX Solution: 2 transistor cell Write FLOTOX Read NMOS 2102-545 Digital ICs Memories 34 B.Supmonchai EEPROM Summary Larger Area than EPROM of the same capacity FLOTOX is inherently larger than FAMOS 2T cells as to 1T cell for the EPROM. Thin oxide is hard to fabricate and expensive. Cost/bit is higher than the EPROMs Higher versatility: in situ programming/erasure Last longer (up to 105 erase/program cycles) but repeated programming can cause VT to drift due to permanently trapped charges in SiO2 2102-545 Digital ICs Memories 35 B.Supmonchai Flash EEPROM: ETOX Device Control gate Floating gate erasure n 1 source Thin tunneling oxide programming n 1 drain p-substrate Many other options … 2102-545 Digital ICs Memories 36 B.Supmonchai Cross-sections of NVM cells Flash 2102-545 Digital ICs EPROM Memories Courtesy Intel 37 B.Supmonchai Erase in a NOR Flash Memory 2102-545 Digital ICs Memories 38 B.Supmonchai Write in a NOR Flash Memory 2102-545 Digital ICs Memories 39 B.Supmonchai Read in a NOR Flash Memory 2102-545 Digital ICs Memories 40 B.Supmonchai NAND Flash Memory Word line(poly) Gate Unit Cell ONO Gate Oxide FG Source line (Diff. Layer) 2102-545 Digital ICs Memories 41 B.Supmonchai NAND Flash Memory Select transistor Word lines Active area STI Bit line contact 2102-545 Digital ICs Source line contact MemoriesToshiba Courtesy 42 B.Supmonchai State-of-the-art NVM 2102-545 Digital ICs Memories 43 B.Supmonchai Read-Write Memories (RAM) STATIC (SRAM) Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential DYNAMIC (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended 2102-545 Digital ICs Memories 44 B.Supmonchai 6-Transistor CMOS SRAM Cell WL V DD M2 M5 M4 Q Q M1 M3 BL 2102-545 Digital ICs M6 BL Memories 45 B.Supmonchai CMOS SRAM Analysis (Read) WL V DD M4 BL Q= 0 M5 V DD M1 Q= 1 V DD Cbit 2102-545 Digital ICs BL M6 V DD Cbit Memories 46 B.Supmonchai CMOS SRAM Analysis (Read) 1.2 Voltage Rise (V) 1 0.8 0.6 0.4 0.2 0 0 2102-545 Digital ICs 0.5 1 1.2 1.5 2 Cell Ratio (CR) Memories 2.5 3 47 B.Supmonchai CMOS SRAM Analysis (Write) WL V DD M4 M5 M6 Q= 0 Q= 1 M1 V DD BL = 1 2102-545 Digital ICs BL = 0 Memories 48 B.Supmonchai CMOS SRAM Analysis (Write) 2102-545 Digital ICs Memories 49 B.Supmonchai 6T-SRAM Layout VDD M2 M4 Q Q M1 M3 GND M5 BL 2102-545 Digital ICs M6 WL BL Memories 50 B.Supmonchai Resistance-load SRAM Cell WL V DD RL M3 BL RL Q Q M1 M2 M4 BL Static power dissipation -- Want R L large Bit lines precharged to V DD to address t p problem 2102-545 Digital ICs Memories 51 B.Supmonchai SRAM Characteristics 2102-545 Digital ICs Memories 52 B.Supmonchai 3-Transistor DRAM Cell BL 1 BL 2 WWL WWL RWL M3 M1 CS X M2 RWL V DD 2 V T X BL 1 BL 2 V DD V DD 2 V T DV No constraints on device ratios Reads are non-destructive Value stored at node X when writing a “1” = V WWL-VTn 2102-545 Digital ICs Memories 53 B.Supmonchai 3T-DRAM Layout BL2 BL1 GND RWL M3 M2 WWL M1 2102-545 Digital ICs Memories 54 B.Supmonchai 1-Transistor DRAM Cell Write: C S is charged or discharged by asserting WL and BL. Read: Charge redistribution takes places between bit line and storage capacitance CS DV = VBL – V PRE = V BIT – V PRE -----------C S + CBL Voltage swing is small; typically around 250 mV. 2102-545 Digital ICs Memories 55 B.Supmonchai DRAM Cell Observations 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. 2102-545 Digital ICs Memories 56 B.Supmonchai DRAM Cell Observations II When writing a “1” into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than VDD 2102-545 Digital ICs Memories 57 B.Supmonchai Sense Amp Operation V BL V(1) V PRE D V(1) V(0) Sense amp activated Word line activated 2102-545 Digital ICs Memories t 58 B.Supmonchai 1-T DRAM Cell Capacitor Metal word line M 1 word line SiO2 Poly n+ Field Oxide n+ Poly Inversion layer induced by plate bias Diffused bit line Polysilicon gate Cross-section Polysilicon plate Layout Uses Polysilicon-Diffusion Capacitance Expensive in Area 2102-545 Digital ICs Memories 59 B.Supmonchai 1T-DRAM SEM SEM of poly-diffusion capacitor 1T-DRAM 2102-545 Digital ICs Memories 60 B.Supmonchai Advanced 1T DRAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate Si Capacitor Insulator Refilling Poly Transfer gate Isolation Storage electrode Storage Node Poly Si Substrate 2nd Field Oxide Stacked-capacitor Cell Trench Cell 2102-545 Digital ICs Memories 61 B.Supmonchai Static CAM Memory Cell Bit Bit Bit Bit Bit Word CAM ••• ••• Word M4 M8 M9 M6 M7 M5 CAM ••• Word CAM Bit ••• CAM S M3 Match int S M2 M1 Wired-NOR Match Line 2102-545 Digital ICs Memories 62 B.Supmonchai CAM ARRAY Hit Logic Address Decoder CAM in Cache Memory SRAM ARRAY Input Drivers Address 2102-545 Digital ICs Tag Sense Amps / Input Drivers Hit Memories R/W Data 63 B.Supmonchai Periphery Decoders Sense Amplifiers Input/Output Buffers Control/Timing Circuitry 2102-545 Digital ICs Memories 64 B.Supmonchai Row Decoders Collection of 2M complex logic gates Organized in regular and dense fashion (N)AND Decoder NOR Decoder 2102-545 Digital ICs Memories 65 B.Supmonchai Hierarchical Decoders Multi-stage implementation improves performance ••• WL 1 WL 0 A 0A 1 A 0A 1 A 0A 1 A 0A 1 A 2A 3 A 2A 3 A 2A 3 A 2A 3 ••• NAND decoder using 2-input pre-decoders A1 A0 2102-545 Digital ICs A0 A1 A3 A2 A2 A3 Memories 66 B.Supmonchai Dynamic Decoders Precharge devices GND VDD GND WL 3 VDD WL 3 WL 2 WL 2 VDD WL 1 WL 1 V DD WL 0 WL 0 VDD f A0 A0 A1 A1 A0 2-input NOR decoder 2102-545 Digital ICs A0 A1 A1 f 2-input NAND decoder Memories 67 B.Supmonchai 4-Input PT Based Column Decoder A0 A1 2-input NOR decoder BL 0 BL 1 BL 2 BL 3 S0 S1 S2 S3 D Advantages: speed (tpd does not add to overall memory access time) Only one extra transistor in signal path Disadvantage: Large transistor count 2102-545 Digital ICs Memories 68 B.Supmonchai 4-to-1 Tree Based Column Decoder BL 0 BL 1 BL 2 BL 3 A0 A0 A1 A1 D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches 2102-545 Digital ICs Memories 69 B.Supmonchai Sense Amplifiers × DV C tp = ---------------Iav large make D V as small as possible small Idea: Use Sense Amplifer small transition s.a. input 2102-545 Digital ICs Memories output 70 B.Supmonchai Differential Sense Amplifier V DD M3 M4 y M1 bit SE M2 Out bit M5 Directly applicable to SRAMs 2102-545 Digital ICs Memories 71 B.Supmonchai Differential Sensing - SRAM V DD PC V DD BL BL V DD V DD EQ M4 y M3 WL i M1 x SE M2 2y 2x 2x x SE M5 SE SRAM cell i V DD Diff. x Sense 2x Amp Output y SE Output (b) two stage differential amplifier (a) SRAM sensing scheme 2102-545 Digital ICs Memories 72 B.Supmonchai Latch-Based Sense Amplifier (DRAM) EQ BL Initialized in its metastable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. BL VDD SE SE 2102-545 Digital ICs Memories 73 B.Supmonchai Case Studies Programmable Logic Array SRAM Flash Memory 2102-545 Digital ICs Memories 74 B.Supmonchai Programmable Logic Array (PLA) Structured approach to random logic “Two level logic implementation” NOR-NOR (Product of Sums) NAND-NAND (Sum of Products) Circuit structure similar to ROM with main difference: ROM: fully populated PLA: one element per min term Importance of PLA has drastically reduced Slow Better optimization techniques (Multi-level logic synthesis) 2102-545 Digital ICs Memories 75 B.Supmonchai Pseudo-NMOS PLA GND GND GND V DD GND GND GND GND V DD X0 X0 X1 X1 X2 AND-plane 2102-545 Digital ICs X2 f0 f1 OR-plane Memories 76 B.Supmonchai Dynamic PLA f AND V DD GND f OR f OR f AND V DD X0 X0 X1 X1 X2 X2 AND-plane 2102-545 Digital ICs f0 f 1 GND OR-plane Memories 77 B.Supmonchai Dynamic PLA: Clock Signal Generation Clock Signal Generation for self-timed dynamic PLA f f f f Dummy AND row f AND Dummy AND row f OR AND tpre teval f AND OR (a) Clock signals 2102-545 Digital ICs (b) Timing generation circuitry Memories 78 B.Supmonchai PLA Layout VDD And-Plane x0 x0 x1 x1 x2 x2 Pull-up devices 2102-545 Digital ICs Memories Or-Plane f GND f0 f1 Pull-up devices 79 B.Supmonchai 4 Megabit SRAM Hierarchical Word-line Architecture 2102-545 Digital ICs Memories 80 B.Supmonchai Bit-line Circuitry Block select Bit-line load ATD BEQ Local WL Memory cell B /T B /T CD CD CD I/O I/O line I/O Sense amplifier 2102-545 Digital ICs Memories 81 B.Supmonchai Sense Amplifier (and Waveforms) I /O I /O Address SEQ Block select ATD ATD BS BEQ SA BS SA Vdd I/O Lines GND SEQ SEQ SEQ SEQ SEQ Vdd DATA Dei SA, SA GND DATA BS Data-cut 2102-545 Digital ICs Memories 82 B.Supmonchai 1 Gigabit Flash Memory From [Nakamura02] 2102-545 Digital ICs Memories 83 B.Supmonchai Number of cells Writing Flash Memory 108 106 104 Read level (4.5 V) 102 100 0V 1V 2V 3V 4V Vt of memory cells Evolution of thresholds Final Distribution From [Nakamura02] 2102-545 Digital ICs Memories 84 B.Supmonchai Charge pump 2kB Page buffer & cache 10.7mm 125mm2 1Gbit NAND Flash Memory 32 word lines x 1024 blocks 16896 bit lines 11.7mm From [Nakamura02] 2102-545 Digital ICs Memories 85 B.Supmonchai 125mm2 1Gbit NAND Flash Memory Technology: 0.13m p-sub CMOS triple-well 1poly, 1polycide, 1W, 2Al Cell size: 0.077m2 Chip size: 125.2mm2 Organization: 2112 x 8b x 64 page x 1k block Power supply: 2.7V-3.6V Cycle time: 50ns Read time: 25s Program time: 200s / page Erase time: 2ms / block 2102-545 Digital ICs Memories From [Nakamura02] 86 B.Supmonchai Semiconductor Memory Trends Quadruple every three year From [Itoh01] 2102-545 Digital ICs Memories 87 B.Supmonchai Trends in Memory Cell Area From [Itoh01] 2102-545 Digital ICs Memories 88 B.Supmonchai Technology Scaling Trends Technology feature size for different SRAM generations 2102-545 Digital ICs Memories 89
