Download No Slide Title

Outline
•
•
•
•
•
•
Introduction
CMOS devices
CMOS technology
CMOS logic structures
CMOS sequential circuits
CMOS regular structures
CMOS logic structures
•
•
•
•
•
•
CMOS logic: “0” and “1”
The MOST - a simple switch
The CMOS inverter
The CMOS pass gate
Simple CMOS gates
Complex CMOS gates
CMOS logic: “0” and “1”
• Logic circuits process
Boolean variables
• Logic values are
associated with voltage
levels:
Output
+V
+V
"1"
VOH
Noise Margin
High
– VIN > VIH  “0”
– VIN < VIL  “0”
VIH
Undefined
region
VIL
• Noise margin:
– NMH=VOH-VIH
– NML=VIL-VOL
Input
Noise Margin
Low
VOL
"0"
0
0
The MOST - a simple switch
p-switch
G
A
p-switch
B
S
D
Y
D
Y
A
B
Y
0
0
1
1
0
1
0
1
bad 0 (source follower)
good 1
?
(high Z)
?
(high Z)
A
B
Y
0
0
1
1
0
1
0
1
?
(high Z)
?
(high Z)
good 0
bad 1 (source follower)
G
A
S
n-switch
n-switch
B
MOSFET’s in digital design
• Important characteristics:
– It is an unipolar device
• NMOS - charge carrier: electrons
• PMOS - charge carrier: holes
– It is a symmetrical device
• Source = drain
– High input impedance (Ig=0)
• Low standby current in CMOS configuration
– Voltage controlled device with high fan-out
The CMOS inverter
VDD
p-switch
VDD
Y
A
Y
n-switch
A
VSS
VSS
A
Y
0
good 1
1
good 0
The CMOS inverter
Inverter DC transfer characteristic
VDD
2.5
2
Y
Vout (V)
2.5/0.25
A
Slope = -1
1.5
Vout=Vin
1
/0.25
Slope = -1
0.5
VSS
0
0
0.5
1
Vin (V)
1.5
2
2.5
The CMOS inverter
substrate
contact (p+)
n+ diffusion
polysilicon
metal
n-well
n-well
contact (n+)
p+ diffusion
The CMOS pass gate
C
C
n-switch
A
Y
A
Y
p-switch
C
C
C
0
0
1
1
A
0
1
0
1
Y
?
?
good 0
good 1
The CMOS pass gate
Regions of operation:
“0” to “1” transition
• NMOS:
– source follower
– Vgs = Vds always:
Pass gate: 0 => 1 transition
Vdd
in
out
1
1
• PMOS:
– current source
– Vout < |VTP|  saturation
– Vout > VTP  linear
t
t
in
• Vout < Vdd-VTN  saturation
• Vout > Vdd-VTN  cutoff
– VTN > VTN0 (bulk effect)
0
0
out
0V
Equivalent for 0 = > 1 transition
Vdd
out
"Current
source"
"Source
follower"
Simple CMOS gates
NAND
A
B
Y
A
0
0
1
1
B
0
1
0
1
Y
1
1
1
0
Simple CMOS gates
NAND 3 inputs
p
p
Y
A
n
B
n
C
n
Pull down <=> 3 on Pull up <=> 1 on
p
"Delay equivalent" inverter
p
n/3
Simple CMOS gates
NAND 3 inputs
p
p
p
Y
A
n
Use transistors
close to the output
for critical signals
Bulk effect
B
n
C
n
Stray capacitance
Simple CMOS gates
Bad: high stray
capacitance and
large area
A
B
C
Good: minimum
stray capacitace
and small area
Shared
source/drain
diffusions
Minimum
distance
Simple CMOS gates
NOR
A
0
0
1
1
B
0
1
0
1
Y
1
0
0
0
Y
A
B
Simple CMOS gates
Tri-state inverter
VDD
E
Y
A
E
E
0
1
Y
high Z
A
Complex CMOS gates
Multiplexer
B
S
A
S
Y
S
0
1
Y
A
B
Complex CMOS gates
Exclusive OR
A
Y
A
0
0
1
1
B
B
0
1
0
1
Y
0
1
1
0
Complex CMOS gates
(A+B)
B
Pull up
A
(A+B) (C+D)
C
(AB)(CD)
AB+CD
(C+D)
D
Y
The NMOS pull-down => inversion
Pull down
NMOS activated by "1" PMOS activated by "0"
AOI
A
C
(AB)
AB + CD
B
D (CD)
AB + CD
Complex CMOS gates
Pull up
A
D
Y
AB
00 01 11 10
00
1
1
1
1
CD 01
1
0
0
0
11
0
0
0
0
01
1
1
1
1
Y
AB
00 01 11 10
00
1
1
1
1
CD 01
1
0
0
0
11
0
0
0
0
01
1
1
1
1
D+ABC
B
C
Y
Pull down
NMOS activated by "1" PMOS activated by "0"
Compound gate
Y = D (A + B + C)
D
D (A + B + C)
A
B
C
Complex CMOS gates
• Can a compound gate be arbitrarily complex?
– NO, propagation delay is a strong function of fanin:
2
t p  a0  FO  a1  FI  a2   FI 
– FO  Fan-out, number of loads connected to the
gate:
• 2 gate capacitances per FO + interconnect
– FI  Fan-in, Number of inputs in the gate:
• Quadratic dependency on FI due to:
– Resistance increase
– Capacitance increase
– Avoid large FI gates (Typically FI  4)
Single-Bit Addition
Half Adder
S  A B
Cout  A B
A
B
Cout
S
Full Adder
A
B
S  A B C
Cout
Cout  MAJ ( A, B, C )
S
C
A
B
Cout
S
Ak
Bk
Ck-1
Ck
Sk
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
1
0
1
1
0
0
1
0
1
0
0
1
1
1
1
0
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
For the Sum Sk
If Ak=Bk then Sk=Ck-1 else Sk=Ck-1
For the carry
If Ak=Bk then Ck=Ak=Bk else Ck=Ck-1
Full Adder Design I
• Brute force implementation from eqns
S  A B C
Cout  MAJ ( A, B, C )
A
A
A
S
C
A
B
B
C
C
MAJ
C
B
C
B
B
A
A
17: Adders
C
B
S
Cout
B
A
B
A
B
C
A
B
C
B
A
28
B
C
A
C
A
B
B
Cout
Full Adder Design II
• Factor S in terms of Cout
S = ABC + (A + B + C)(~Cout)
• Critical path is usually C to Cout in ripple adder
MINORITY
A
B
C
Cout
S
Cout
17: Adders
29
S
Complex CMOS gates
Adder
CARRY = (A+B)C + AB
SUM = (A+B+C)CARRY +ABC
CARRY
A
B
C
B
A
A
C
B
B
A
C
SUM
C
B
C
A
B
B
A
A
B
C
A