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VLSI Prof. Vojin G. Oklobdzija References (used for creation of the presentation material): [1] Mead, Conway, “Introduction to VLSI Systems”, Addison Wesley Publishing. [2] Glasser, Dobberpuhl, “The Design and Analysis of VLSI Circuits”, Addison Wesley Publishing. [3] Weste, Eshraghian, “Principles of CMOS VLSI Design”, Addison Wesley Publishing. [4] Shoji, “CMOS Digital Circuits Technology”, Prentice Hall. Historical Overview • • • • nMOS era: 1970-85 Pass-transistor design CMOS existed early but took off 1985 on Domino CMOS, 1982 – NORA – DCVSL • CPL, DPL – DCVS-PG – SRPL – LEAP • SOI-CMOS Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 2 n-MOS Design Era 1970-85 LSI started with nMOS: • pass-transistor design experience: - Flourished at the beginning of the nMOS era (popularized by Mead-Conway book) - Allows high density layout and compact design style - Fast: outperforming gate based design - Low in power • Drawbacks: – Not compatible with existing design tools – Exhibiting testability and reliability problems Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 3 Review of CMOS Prof. Vojin G. Oklobdzija CMOS Basics Vdd Karnaugh Map of Function F ( A + B) A F 0 1 0 1 1 1 1 0 F B (A A B) B C Function F and its Dual Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 5 CMOS Basics Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 6 CMOS Basics covering ones : D( A + B C ) B A D C D 0 1 1 0 0 1 covering zeroes : D + A (B +C) C 0 0 0 0 1 0 0 0 A A Fall 2004 0 B F B 1 D D Prof. V.G. Oklobdzija: High-Performance System Design 7 CMOS Basics A complex path example: VDD E B D A C Output A B C D E Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 8 CMOS Basics Primitive gates: Fall 2004 More complex blocks are realizable in CMOS Prof. V.G. Oklobdzija: High-Performance System Design 9 CMOS Deficiencies: Various remedies: Fall 2004 Muli-Input NOR function in CMOS is slow Prof. V.G. Oklobdzija: High-Performance System Design 10 CMOS Deficiencies and Remedies Faster, one-level realizations of XOR function XOR A A B AB B + AB AB + AB B (a) Fall 2004 (b) Prof. V.G. Oklobdzija: High-Performance System Design 11 CMOS Deficiencies and Remedies XNOR Faster, one-level realizations of XOR function A AB + AB AB + AB B Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 12 CMOS Basic Inverter Transfer function: VDD VOH Logic voltage levels are VOH VIH and VOL and VIL and VIH Vout VIL The inverter transfer function lie within the shaded region VOL 0 VOL VIL VIH VOH VDD Vin Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 13 CMOS Basic: Inverter Characteristic p “ON” n “OFF’’ BOTH p & n “ON” A B VDD 0.5VDD C D 0 0 Fall 2004 p ”OFF” n ”ON” Vtn 0.5VDD Leakage Currents E VDD + Vtp VDD Prof. V.G. Oklobdzija: High-Performance System Design 14 CMOS Basic: Inverter Characteristic VDD VDD T2 V0(t) Vin(t) T1 t CL + VDD 0 t + VDD 0.9 VDD 0.1 VDD t td tf Fall 2004 tr Prof. V.G. Oklobdzija: High-Performance System Design 15 CMOS Basic: Inverter Characteristic Transistors during the transition Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 16 CMOS Basic: Inverter Switching VDD p-DEVICE VDD p-DEVICE t=0 Ic Ic CL R c VO n-DEVICE CL VO n-DEVICE SATURATION : VO VDD Vin VDD p-DEVICE LINEAR : 0 VO VDD Vin VDD p-DEVICE R c Ic Ic t=0 CL n-DEVICE SATURATION Fall 2004 VO CL n-DEVICE VO LINEAR Prof. V.G. Oklobdzija: High-Performance System Design 17 CMOS Basic: Power tp • During the static state there is no current VDD V 0 tf • Current is only present during transistion: - Short circuit current (crow-bar current) - Charging and discharging of the output capacitor - Leakage Current Fall 2004 tr t VDD V 0 t VDD I 0 Prof. V.G. Oklobdzija: High-Performance System Design t 18 CMOS Basic: Power PCMOS=kCLV2DDfo This is an E=mc2 of low-power design There are three ways to control power: - Reducing Power-Supply Voltage (most effective !!) - Reducing the switching activity - Reducing k (various ways) CL (technology scaling etc.) - Reducing the required frequency of operation (?) Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 19 CMOS Basic: Delay • Which one of the three designs is the fastest ? • How can we find this out without simulation ? a7 Case 1 CL a0 (a) a7 Case 3 a7 a6 a5 a4 a3 a2 a1 CL a0 (c) Case 2 a4 CL a3 a0 (b) Fall 2004 Learn about Logical Effort ! Prof. V.G. Oklobdzija: High-Performance System Design 20 CMOS Basic: Delay Charge: Ic Cin1 Discharge Id Fall 2004 Cout Cin2 Discharge Id Prof. V.G. Oklobdzija: High-Performance System Design 21 CMOS Basic: Delay RNOR Ic Id RND7 Id Cin1 Cin2 RND2 Cout Delay can be approximated with: RND7Cin1+RNORCin2+RND2Cout Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 22 CMOS Basic: Delay Delay of a signal path in CMOS logic is dependent on: • Fan-in of a gate – Represented as a resistance of the pullup/down transistor path of the gate • Fan-out of a gate – Represented as a capacitive load at the output • Number of CMOS blocks in the path. • Wire delay connecting various blocks. Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 23 CMOS Basic: Delay Delay of a signal path in CMOS logic can be reduced by: • Making the transistors larger in order to minimize resistance of a pull-up/down path in the gate • Making the transistors smaller in order to minimize the capacitive load of each gate • Reducing the number of CMOS blocks in the path. • Bringing the blocks closer and/or choosing the less wire intensive topology. – Note that these requirements are often contradictory Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 24 CMOS Basic: Delay • How to estimate delay and critical timing in CMOS circuits ? • How to determine the proper transistor sizing in order to make a compromise with contradicting requirements ? • How to choose the right circuit topology ? The Answer: “Logical Effort” Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 25 Pass-Transistor Design Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 26 Pass-Transistor Design Another way of looking at Karnaugh Map: AND function A A B F 0 1 0 0 1 1 1 0 F B B A Fall 2004 B Prof. V.G. Oklobdzija: High-Performance System Design B 27 Pass-Transistor Design A X F Y A Two-variable function Fall 2004 X 0 0 1 1 0 0 1 1 B B B B B B B B Y 0 1 0 1 B B B B 0 1 0 1 B B F 0 A A 1 AB AB AB AB AB AB A+B A B B B A B A B B B Prof. V.G. Oklobdzija: High-Performance System Design 28 Pass-Transistor Design “Threshold Voltage Drop” problem: A=Vdd + V th - B=Vdd Fmax = Vdd-Vth B Vdd Vdd Vdd + V V + th th -- Fmax = Vdd-Vth Cout Cout A (a) Fall 2004 (b) Prof. V.G. Oklobdzija: High-Performance System Design 29 Pass-Transistor Design Solving the “Threshold Voltage Drop” problem in CMOS: +Vdd A=Vdd + V th Vdd + V th Fmax= Vdd In=Vdd ON Vdd - + Cout Cin Vdd A=0V (a) Fall 2004 (b) Prof. V.G. Oklobdzija: High-Performance System Design 30 Pass-Transistor Design A A B B P0 P1 F(A,B) P2 P3 Fall 2004 Function Generator Prof. V.G. Oklobdzija: High-Performance System Design 31 Pass-Transistor Design Full 1-bit Adder A S A A S CO A A CO B Fall 2004 B C C Prof. V.G. Oklobdzija: High-Performance System Design 32 Pass-Transistor Design Compact ALU Example (IBM PC/RT) Circ. 1984 Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 33 Control Lines A - inputs Odd Operation Output Control B - inputs Even Odd A Even K1 K2 Qn A B B Odd Even 0 0 0 0 1 1 0 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0 1 Arithmetic A+B Add A+B+1 A-B Subtract 0 0 1 0 1 1 0 1 0 0 1 0 1 B-A Subtract 0 0 1 1 0 0 1 0 1 1 0 0 1 B+1 Increment 0 0 1 1 1 0 0 0 1 1 0 0 1 2s compl 0 0 1 1 1 0 0 1 0 0 1 0 1 Increment 0 0 1 0 1 1 0 1 1 0 0 0 1 2s compl 0 0 1 1 0 0 1 1 1 0 0 0 1 +1 A+1 +1 Logical 1 1 1 0 0 0 0 0 0 0 0 0 0 0 B 1 1 0 0 0 0 0 0 1 0 1 0 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1 0 1 1 0 1 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 1 0 1 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 0 1 0 1 0 1 0 1 1 1 1 0 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1 1 1 1 0 0 1 0 1 1 0 1 0 1 1 1 1 0 1 0 1 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 1 0 1 0 1 1 0 1 0 1 0 1 0 0 1 0 1 1 1 0 A Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 34 Pass-Transistor Design Function Generator VH f A Compact ALU Example (IBM PC/RT) B A B K2 CO K2 VH CO CI K2 A K1 A B B Carry Generator Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 35 Using Pass-Transistor Design to Speedup Addition Fall 2004 Prof. V.G. Oklobdzija: High-Performance System Design 36