Download Statistical Timing Analysis with Correlated Non

Statistical Full-Chip Leakage
Analysis Considering Junction
Tunneling Leakage
Tao Li
Zhiping Yu
Institute of Microelectronics
Tsinghua University
Outline

Motivation

Junction Tunneling Leakage – Circuit Level Analysis
– Simple inverter
– Multi-input gate

Statistical Full-Chip Leakage Analysis Technique
– Modeling of process-induced parameter variations

PCA & ICA
– Sum of leakage components

Experimental Results

Summary
2
Leakage and Process Variations
Leakage power becomes a major component of
the total power.

Process variation has a significant impact on leakage.
Power (W)

250
200
150
Leakage Power
Active Power
100
50
0
0.18 μm
0.25
0.18
0.09 μm
0.13
0.1
65 nm
Feature Size
Scale Down
3
Major Leakage components

Subthreshold leakage

Gate oxide leakage

Junction tunneling leakage
Subthreshold
Leakage Isub
Gate Leakage Igate
Gate
Source
Drain
n+
n+
Bulk
Junction tunneling leakage
4
Overview of Related Works

Previous works on statistical full-chip
leakage computation
– Computation of PDF of full-chip leakage
Approximate process variations as
Gaussian distributions
 Finding full-chip leakage by summing up
independent lognormals
 R. Rao ISLPED03,H. Chang ICCAD 03,
H. Chang DAC05, X. Li DAC06, et al.


Most of the previous works ignored
– Effect of Non-Gaussian parameters
– Junction tunneling leakage
5
Outline

Motivation

Junction tunneling leakage – Circuit level analysis
– Simple inverter
– Multi input gate

Statistical Full-chip leakage analysis technique
– Modeling of process-induced parameter variations

PCA & ICA
– Sum of leakage components

Experimental Results

Summary
6
Simple Inverter

Vdd
When input = 0V
– NMOS: maximum I junc & Isub
 Can be independently
calculated and added
for total leakage
– PMOS: gate oxide leakage
– small and ignored
Vdd
0
I junc
Isub
Vdd

When input = Vdd
– NMOS: gate oxide leakage
– PMOS: subthreshold
leakage and junction
tunneling leakage
Isub & I junc
Vdd
0
Igate
7
Multi input gate: general approach

If all inputs have a high state
– Analysis is similar to the that of the inverter

At least one input is low
– Combination of I junc , I gate ,and I sub
– Approach: distinguish 6 different scenarios
noutput
0
VDD
VDD
noutput
tt
0
na
tm 0
nb
tb V
DD
noutput
tt
0
na
tm V
DD
nb
tb
0
tt V
DD
na
tm 0
nb
tb 0
noutput
noutput
tt
VDD
na
tm V
DD
nb
tb
0
tt V
DD
na
tm
0
nb
tb VDD
noutput
tt
na
tm
nb
tb
8
Computation of Total Chip Leakage

Total leakage current of a chip:
Ngate
Ngate
I total   ( I sub  I gate  I junc )  
j 1

j 1 input _ state _ i
( Pi , j I ij ,sub  Pi , j I ij ,gate  Pi , j I ij , junc )
Pi , j : probability of input vector state i of the jth gate
I total can be either the leakage for a fixed input vector or the
average leakage current

Input pattern independent approach
– Direct computation: 2k input vector states for a k-input gate
– Applying dominant states of I ij ,sub  I ij ,gate  I ij , junc

Leakage of stack at state i is not always independent
– Interactions of Isub, Igate and Ijunc need to be considered
– Analyzing leakage current of stack by input state
9
Dominant States of Leakage Current

Interaction between Isub and Igate
(a) I total  I sub  I gate
(b) I total  I sub
(c) I total  I gate

Case (a) (c): dominate states of Igate

Case (a) (b): dominate states of Isub
NMOS-Transistor Stack
D. Lee et. al. at DAC03
C. Oh et. al. at DAC99
D. Lee et. al. at DAC03

Dominant states of junction tunneling leakage Ijunc
– States with the “on” transistors connected to the output node
(stack effect )
– Only k dominant states for a k-input gate
10
Results: Leakage estimation for 4-NAND
The error of the proposed analysis method over SPICE
4
3
% Error
2
1
0
-1
-2
-3
Total Leakage (nA)

14
12
10
8
6
4
2
0
0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Average ~1.5% over all input states

Maximum error = 4.5% @1110
11
Outline

Motivation

Junction tunneling leakage – Circuit level analysis
– Simple inverter
– Multi input gate

Statistical Full-chip leakage analysis technique
– Modeling of process-induced parameter variations

PCA & ICA
– Sum of leakage components

Experimental Results

Summary
12
Proposed Analysis Method Highlights
Incorporates both Gaussian
and non-Gaussian parameters
Non-Gaussian and Gaussian variables
transformed
to independent basis with PCA/ICA
Inputs are moments of varying
process parameters
Easier to obtain moments from
process data files
Fast algorithm for the sum up of
leakage components
Three kinds of leakage components
are considered
Uses closed form PDF/CDF
expressions
Moments matching-based
PDF/CDF extraction
13
Outline

Motivation

Junction tunneling leakage – Circuit level analysis
– Simple inverter
– Multi input gate

Statistical Full-chip leakage analysis technique
– Modeling of process-induced parameter variations

PCA & ICA
– Sum of leakage components

Experimental Results

Summary
14
Experimental Results

Comparison of our results with Monte Carlo simulations

Comparison with Gaussian modeling of parameters
Benchmark
Name
#Cells
Our Method Error ((Our-MC)/MC)%
#Grids
µ
σ
95% Pt
5% Pt
Gaussian Error ((Old-MC)/MC)%
µ
σ
95% Pt
5% Pt
C7552
5235
64
-1.63
3.02
3.84
3.91
6.32
23.44
24.66
4.56
C5315
3768
64
-1.07
-2.82
-4.09
-3.68
5.69
17.56
20.31
4.89
C6288
2552
16
-1.15
-2.14
3.52
3.61
5.98
14.63
14.89
3.11
C3540
2491
16
0.71
1.56
2.97
2.88
4.96
10.23
15.34
-3.16
C2670
1854
16
-0.81
1.34
2.90
2.77
4.78
8.84
11.13
2.34
C1908
1197
16
-0.64
-0.98
-2.45
2.12
3.45
8.02
8.98
4.34
C880
556
4
-0.23
-0.59
-1.26
-1.32
2.12
6.14
9.32
1.23
C432
273
4
-0.07
-0.23
-0.98
-0.84
1.29
5.99
4.14
-2.01
15
Outline

Motivation

Junction tunneling leakage – Circuit level analysis
– Simple inverter
– Multi input gate

Statistical Full-chip leakage analysis technique
– Modeling of process-induced parameter variations

PCA & ICA
– Sum of leakage components

Experimental Results

Summary
16
Summary

A fast approach to compute total leakage current
– Considering I junc , I gate ,and Isub
– Average error 1.5%

Both Gaussian and Non-Gaussian parameters are
considered
– PCA and ICA are employed as preprocessing steps

Sum the leakage to get a final result

Algorithm has a complexity of
O G 
17
Thanks!
18