Download Electrical Engineering Student Senior Capstone Project: A MOSIS

Electrical Engineering
Student Senior Capstone Project:
A MOSIS FFT Processor Chip-Set
Peter M. Osterberg & Aziz S. Inan
Donald P. Shiley School of Engineering
University of Portland
ASEE 2011 (Vancouver, BC)
Outline
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Introduction
The MOSIS Educational Program (MEP)
FFT overview
Project description
Conclusion
ASEE 2011 (Vancouver, BC)
Introduction
• Undergraduate EE student senior capstone design project
“success story” from the University of Portland using the
MOSIS Educational Program (MEP)
• EE students: Neil Tuttle, Ziyuan Zhang, Sandra Pellecer
• Designed, built, tested, and demonstrated a successful 10kHz
4-bit, 8-sample FFT system based on a MOSIS chip-set
• Highly effective pedagogical experience
• MEP plays crucial role in leveraging successful EE senior
capstone design projects
ASEE 2011 (Vancouver, BC)
The MOSIS Educational Program (MEP)
• MOSIS = MOS Implemetation Service
• Free integrated circuit mask-making, fabrication and packaging
services to university engineering academic programs
• MEP is based at the University of Southern California
• Multi-Project Wafer (many student projects on same wafer)
• 0.5um N-Well CMOS process (ON Semiconductor, Dupont)
• Digital logic gate standard cell library: NAND, NOR, D-FF, MUX, etc
• Chip sizes: units of 1.5mm x 1.5mm
• 40 pin DIP package
• University of Portland has been participating annually since 1997
ASEE 2011 (Vancouver, BC)
Fast Fourier transform (FFT) Overview
• FFT utilizes efficient “divide-and-conquer butterfly” parallelized
algorithm to compute the Discrete Fourier Transform (DFT)
• O[nlog(n)] vs O[n2], where n=number of samples
• Used in digital signal processing applications to analyze, filter,
and generate digital signals
ASEE 2011 (Vancouver, BC)
Project Description:
CAD Tools Used for Chip-Set Design
• Chip logic simulation: B2Logic (Beige Bag Software, Inc)
• Chip layout: L-Edit (Tanner EDA)
• FFT system simulation: Matlab (The Mathworks, Inc)
ASEE 2011 (Vancouver, BC)
Project Description: High-level Dataflow Diagram
• Divide-and-conquer “butterfly” algorithm (n=8): 4x2 butterfly
calculation, 2x4 butterfly calculation, 1x8 butterfly calculation
ASEE 2011 (Vancouver, BC)
Project Description: High-Level FFT Chip-Set Block Diagram
CHIP2
CHIP1
2-Point
Butterfly
Calculation
4-Point
Butterfly
Calculation
2-Point
Butterfly
Calculation
Input
Data
Input
Registers
and
Reordering
Output
Registers
and
MUX
Output
Data
Input
Registers
2-Point
Butterfly
Calculation
4-Point
Butterfly
Calculation
2-Point
Butterfly
Calculation
ASEE 2011 (Vancouver, BC)
8-Point
Butterfly
Calculation
Output
Registers
and MUX
Project Description:
MOSIS Chip 1 Detailed Block Diagram
ASEE 2011 (Vancouver, BC)
Project Description:
MOSIS Chip 1 B2Logic Schematic
ASEE 2011 (Vancouver, BC)
Project Description:
MOSIS Chip 1
L-Edit layout
3mm x 3mm
2500 gates
DIP package pin-out
ASEE 2011 (Vancouver, BC)
Project Description:
MOSIS Chip 2 Detailed Block Diagram
ASEE 2011 (Vancouver, BC)
Project Description:
MOSIS Chip 2 B2Logic Schematic
ASEE 2011 (Vancouver, BC)
Project Description:
MOSIS Chip 2
L-Edit chip layout
3mm x 3mm
2500 gates
DIP package pin-out
ASEE 2011 (Vancouver, BC)
Project Description:
Chip-Set Simulation Timing Diagram
ASEE 2011 (Vancouver, BC)
Project Description:
FFT Test System
LCD
PC
PIC1
RS232
CLK
CHIP1
I2C
Analog
Input
PIC2
CHIP2
Test system block diagram
Test system circuit schematic
ASEE 2011 (Vancouver, BC)
Project Description:
Final FFT Project
ASEE 2011 (Vancouver, BC)
Project Description: FFT System Input/Output
Results (input sine wave frequency=3.6kHz)
Matlab simulated I/O
ASEE 2011 (Vancouver, BC)
Actual I/O
Conclusions
• Undergraduate EE student senior capstone design project
“success story” using the MOSIS Educational Program (MEP)
• Designed, built, tested, and demonstrated a successful 4-bit, 8sample 10kHz FFT test system based on a MOSIS chip-set
• Achieved “first-silicon” success
• Largest MOSIS chip-set designed to date at University of Portland
• Effective and challenging pedagogical experience for EE senior
students
• MEP plays crucial role in leveraging successful, sophisticated and
satisfying EE senior capstone design projects
ASEE 2011 (Vancouver, BC)
Any
questions?
ASEE 2011 (Vancouver, BC)