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Transcript

Development of the Bandgap Voltage Reference Circuit, Featuring DynamicThreshold MOS Transistors (DTMOSTs) in 0.13um CMOS Technology . Vladimir Gromov Group of microelectronics NIKHEF, Amsterdam, the Netherlands Highlights: 1. The 0.13um CMOS Technology. 2. Implementation of Voltage Bandgap Reference in the 0.13um CMOS Technology. 3. Dynamic-Threshold MOS Transistors (DTMOST) structure. Features, characterization, modeling. 4. Circuit submitted in the experimental run. 5. Conclusions. Features of the 0.13um CMOS Technology in respect to the 0.25um CMOS . • Reduced physical thickness of the gate oxide. • • Fine pitch of lithography. • • Supports many metal layers. Support a wide range of new devices of which Triple-well NFET, and high-quality resistors are the most important. High production cost. • • • Reduced power supply voltage Vdd=1.2V. Devices in this process are extremely robust to radiation damages (there is no need for the gatearound geometries). Standard commercial libraries cells become suitable for our applications. Allows to reduce areas of the devices as to design high-speed high-integrated circuits. • Easies wiring on the design . • Let us reduce substrate noise and make the design much more robust in the mixed-signal environment. . • Some conventional circuits do not fit into the reduced power rails. Voltage Reference Circuit. • Requirements: • The reference voltage must be insensitive to temperature variations. • The reference voltage must be insensitive to the power supply voltage variations. • The reference voltage must be insensitive to the fabrication process variations. Classical voltage summing Bandgap Reference . Vdd Vdd Vref KR PTAT I I R CTAT D 1.161 nD These diodes are p-diffusion in N-well structures. 1.5 Vdd=1.2V 1.12V 6 V1 5 10 T 1 Vg(T=0)=Eg(T=0)/e=1.12V, 1 Where Eg(T)Tis0.002 energy gap between Conduction 6Band and V1 5 10 T 1 T 0.0013 Valence Band in silicon. 0.5 0 0 0 0 50 100 150 200 T 250 300 350 400 400 Principle of operation of the Bandgap Reference circuit. Diode current-to-voltage characteristics are Shockley equations. Vdd Vdd I2(V,T)=Io(T)*[exp(V *e/kT) –1] I1(V,T)=n Io(T)*[exp(V *e/kT) –1] Vref 10 5 KR I I V2-V1 D V nD D I2 I1 R 0 V2 V 8 I( v Tnom )I1, I2 6 5 10 I( v Tnom ) 0 0.5 0.55 0.6 0.65 0.5 n D V1 0.7 0.75 Vv 0.8 Diode voltage-to-current characteristics are Shockley equations. V2(I,T)=kT/e*ln[I/Io(T)] In this architecture I1=I2=I therefore V1(I,T)=kT/e*ln[I/(n*Io(T))] ln(A)-ln(B)=ln(A/B) V2(I,T)-V1(I,T)=kT/e [ln(I/Io(T))- ln(I/(n*Io(T))]= kT/e * ln(n) I= [V2(I,T)-V1(I,T)]/R=[kT/e * ln(n)]/R 0.8 V1, V2 V1( i Tnom 8 ) V1( i Tnom 1 ) 0.7 Current is proportional to absolute temperature PTAT 0.6 0.6 0 7 1 10 2 10 6 4 10 6 10 6 Ii 6 8 10 6 10 5 Voltage summing Bandgap Reference, featuring DTMOST structures. Vdd Vdd Vref KR PTAT I I R CTAT In place of diodes new structures have been used. 1.5 1.5 Vdd=1.2V Vg(T=0)=0.43V, F1( z ) (z 273 ) 0.00072 1 1000 is effective Bandgap voltage for (z 273 ) 0.00072 the DTMOST structure. F1( z ) 1000 0.43V 0 0.5 0 0 0 50 100 150 z 200 273 250 300 320 Dynamic-Threshold MOS Transistors (DTMOST) structure. Anne-Johan Annema (1999) Source Gate metal + oxide Drain P-diffusion P-diffusion Substrate N-well contact Floating N-well (substrate) 2.5 10 5 2 10 5 1.5 10 m4 j2 5 Source Gate N well U I, A Conventional diode structure DTMOST structure m3 j2 1 10 5 Drain I 5 10 10 6 Uthr DIODE = 650mV Uthr DTMOST = 200mV 7 0 0.1 0.1 0.2 0.3 0.4 m4 m3 j1 j1 U, Volts 0.5 0.6 0.7 0.8 0.8 Characterization of the DTMOST structures. Keithley 487 Picoammeter/ voltage source Heraeus Temperature chamber Heraeus Thermometer Experimental set-up. The DTMOST’s Current-to-voltage characteristics at various temperatures. 0.5 10 5 Voltage across the DTMOST at various currents as a function of temperature. Temp=80ºC Temp=70ºC I, k80 A j2 6 4 10 Estimated Bandgap voltage ≈ 410 mV ≈ Reference Voltage 400 k70 j2 U, mV k60 j2 BG i1 k50 3 10 6 j2 BG i 2 300 k40 j2 Temp=0ºC BG i3 k30 j2 6 2 10 k20 j2 I=2µA F1( z ) Linear fits F2( z ) k10 j2 F3( z ) 200 I=1µA k0 6 j 2 1 10 I=0.5µA 100 10 7 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 0.21 0.22 0.23 0.24 0.25 0.26 0.27 0.1 k80 j1 U, Volts 0.27 250 200 150 100 50 BG BG BG z z z i0 i0 i0 Temp, ºC 0 50 100 Characterization of the DTMOST structures (exponential behaviour). The DTMOST’s Current-to-voltage characteristics. 2.5 10 1 10 5 4 Exponential fit function I(U)=37 10-10 [EXP(30 U)-1] I, A Conventional diode configuration DTMOST configuration Region of 5 exponential m4 j (“ideal 2 diode”) behaviour m3 j2 100mV ….220mV 1 10 1 10 I, A 1 10 f( x ) 1 10 Exponential fit function I(U)=30 10-10 [EXP(30 U)-1] 5 DTMOST 6 Exponential behaviour range 0.1µA…2µA k20 j2 6 ff( x ) 7 10 1 10 7 0 0.01 0.1 0.2 0.3 0.4 m4 m3 x U j, Volts 1 j1 0.5 0.6 0.7 0.8 0.8 1 10 7 1 10 8 0.1 0.12 0.14 0.16 0.18 0.2 x j1 U,k80Volts 0.22 0.24 0.26 0.28 0.3 Modeling of the DTMOST structures in SPECTRE. // DEVICE 1 //simulator lang=spectre insensitive=yes .model DTMOST1 diode + level=1 isw=0.0000e+00 n=1.34e+00 + rs=0.000e-00 ik=2.7400e+09 ikp=1.0000e-08 + ibv=1.0000e-09 trs=1.0000e-03 eg=0.225 + tnom=0.000e+00 xti=6.6 tlev=1.0000e+00 + area=1.000e+00 perim=1.00e+00 cjo=7.5000e-15 + mj=1.0000e+00 vj=3.3000e-01 cjsw=0 + mjsw=1.000e+00 vjsw=4.3000e-01 is=1.62e-09 + bv=1.3100e+01 cta=8.0000e-04 ctp=1.0000e-03 + pta=0.00 ptp=2.0000e-03 fc=0.99 + tlevc=1.000+00 imax=1e+14 gap1=0 gap2=0 The DTMOST’s Current-to-voltage characteristics. I, A k80 j2 k60 4 10 j2 Measured points 6 k40 j2 Results of simulation in Affirma Spectre k20 j2 6 3 10 k0 j2 s80 i1 s60 2 10 6 i1 s40 i1 s20 i1 6 1 10 s0 i1 0.1 0.11 0.12 0.13 0.14 0.15 0.16 0.17 0.18 0.19 0.2 k80 k80 k80 k80 k80 s80 s60 s40 s20 s20 j1 j1 j1 j1 j1 i0 i0 i0 i0 i0 U, Volts Reference voltage (Vref) as a function of temperature. 392.25 Vref≈393mV 393 392 391 UC2 i1 120 IC2 i1 390 Diode model (CADENCE simulations). 389 388.76 388 0 0 10 20 30 40 i1 10 i1 10 Temp, ºC 50 60 70 80 80 0.21 0.22 The circuit. Main Specifications (simulations): Reference voltage: 393mV Temperature sensitivity: ±1.5mV (within a temperature range from 0ºC to 80ºC ). Shift of the Reference voltage caused by supply voltage variations: ±0.25mV (if the supply voltage varies in range from 0.9V to 1.4V ). Power consumption: 60uW (50uA @1.2V) Spread of the Reference voltage due to fabrication process variations: σ=1.2mV. Occupied area on the chip:250um vs 60um Layout of the DTMOST structures. Source T <1:9> Gate N well w=11.7394u l=600n nf=1 m=1 Drain T <1:36> Source w=11.7394u l=600n nf=1 m=1 N well Drain The experimental chip (NIKHEF part). (the chip was submitted in CuTe2 MPW run on May 10, 2004.) 4-channel Preamp/Shaper/Buffer circuit for silicon microstrip sensors. Bandgap voltage Reference, Featuring DTMOST devices. The circuit features conventional NFET devices. 4-channel Preamp/Shaper/Buffer circuit for silicon microstrip sensors. The circuit features Triple-well NFET devices. 2mm Conclusions: • The 0.13um CMOS Technology provides designers with a wide set of attractive options, in particular, those who develop electronics to operate in high radiation environment. • The Voltage Bandgap Reference circuit needs revision in order to fit into the reduced power supply voltage range of the technology. • Dynamic-Threshold MOS Transistors (DTMOST) are to replace diodes in the classical Voltage Bandgap Reference circuit as to be suited for the reduced power supply range . • After characterization and modeling of the DTMOST structures, the circuit was designed and submitted in CuTe2 MPW run on May 10, 2004 with turnaround time of 5 months. Preamplifier In Shaper Gain=1000 Gain=2000 Dummy Preamplifier Gain=1000 Out The Preamp/Shaper circuit. Main specifications: 1) Rise time of the output signal: 14ns. 2) ENC (Cd=15pf) : 900e. 3) Charge sensitivity: 100mv/2fC(1MIP). 4) Power consumption: 1.7mW per channel. 5) Dynamic range: 0…10MIPs. The charge-sensitive preamplifier. The Shaper. Principle of operation of the Bandgap Reference circuit. Diode current-to-voltage characteristics are Shockley equations. Vdd Vdd I2(V,T)=Io(T)*[exp(V *e/kT) –1] I1(V,T)=n Io(T)*[exp(V *e/kT) –1] Vref 10 5 KR I I V2-V1 D V nD D I2 I1 R 0 V2 V 8 I( v Tnom )I1, I2 6 5 10 I( v Tnom ) 0 0.5 0.55 0.6 0.65 0.5 n D V1 0.7 0.75 Vv 0.8 Diode voltage-to-current characteristics are Shockley equations. V2(I,T)=kT/e*ln[I/Io(T)] In this architecture I1=I2=I therefore V1(I,T)=kT/e*ln[I/(n*Io(T))] ln(A)-ln(B)=ln(A/B) V2(I,T)-V1(I,T)=kT/e [ln(I/Io(T))- ln(I/(n*Io(T))]= kT/e * ln(n) I= [V2(I,T)-V1(I,T)]/R=[kT/e * ln(n)]/R 0.8 V1, V2 V1( i Tnom 8 ) V1( i Tnom 1 ) 0.7 Current is proportional to absolute temperature PTAT 0.6 0.6 0 7 1 10 2 10 6 4 10 6 10 6 Ii 6 8 10 6 10 5 » Content. Slide#1. Good morning. I am Vladimir Gromov from microelectronics group of NIKHEF, Amsterdam, the Netherlands. I am delighted to be here today to tell you about a novel circuit proposed by our group. Namely my talk is entitled as “Development of the Bandgap Voltage Reference Circuit, Featuring Dynamic-Threshold MOS Transistors (DTMOSTs)in 0.13um CMOS Technology “. Slide#2. These are highlights of the talk. I will start with a brief description of the features of the 0.13um technology. Then I will tell you why it is not easy to implement classical Voltage Bandgap Reference in this Technology. Further I will tell you about a new device called Dynamic-Threshold MOS Transistors (DTMOST). Features of this device, characterization approach and modeling will be discussed. I will demonstrate you a complete Bandgap Voltage Reference Circuit, Featuring Dynamic-Threshold MOS Transistors (DTMOSTs) circuit that we submitted in the experimental MPW run on May 10 2004. Finally I will draw some conclusions. Slide#3. Since one year ago we have joined efforts of CERN microelecronics group to start prototyping in a new 0.13um CMOS technology. This technology offers a set of features attractive for analog designers. …………………………………………………. Because of the reduced thickness gate oxide isolation does not stand voltage higher than 1.2V. It means that the power supply voltage is limited to 1.2V and any design in this technology is confined in this dynamic range . Some conventional circuits although do not fit into the reduced power rails. Bandgap voltage reference is one of them. Slide#4. Voltage Reference Circuit, in general, is an important building block for many architectures. It is a key component for high quality A/D and D/A converters, it is often used when a stable bias voltage or power supply source is needed. A High Quality Reference circuit is to meet the following requirements: …….. Slide#5.Voltage summing Bandgap Reference is a commonly used architecture in chip design. It consists of two diodes of different sizes (formed by p-diffusion in N-well structures) , two resistors and an OPAMP to control a pair of identical current sources in the feedback. Operation of the circuit rely on two basic features. Number one: for a given current voltage drop on a diode is conversely proportional to absolute temperature (CTAT). In the vicinity of the absolute zero temperature it approaches value called BandGap voltage (1.12V). This value is determined by energy gap between Conduction Band and Valence Band and constitutes a built-in fundamental in silicon . Number two: because of the exponential character of the diode’s current-to-voltage characteristics current through the diodes in the architecture is proportional to absolute temperature. By summing of the voltage drop on the diode with the current determined voltage drop on the resistor a temperature insensitive reference voltage is delivered when the slopes of the curve are properly adjusted. The reference voltage gets the value very close to the BandGap voltage. In 0.13um CMOS technology gap between the reference voltage and the power supply voltage becomes so narrow that voltage left for the current sources is not enough to keep the transistors in saturation mode. I makes the whole concept to fail. Slide#6. In 1999 Anne-Johan Annema proposed a new structure to substitute the conventional diode in the Bandgap architecture. It is in fact a p-channel MOS (PMOST) transistor with gate, drain and substrate contacts connected together. This device behaves similar to a conventional diode with an exception . It needs far lower bias voltage to operate. In this combination the current sources do not suffer from the shortage of voltage any more. Slide#7. Let us take a closer look at the new structure. This device can be seen as a PMOST where every change in gate-source voltage makes substrate-source voltage to change which in turn effects the threshold of the transistor. In other words the signal modulates the threshold that is what we call dynamic-threshold transistor. Drain current in this device is primarily determined by voltage across the source-substrate junction, which results in an exponential current-to-source characteristics of the device. The DTMOST’s curve resembles the curve for a conventional diode but shifted in the low-voltage region. That is why we can call it a low-voltage diode. Another feature of this device is that the matching of the DTMOST's is about twice as good as the matching of PMOSTs of the same size operating at the same current. Moreover batch-to-batch variations of DTMOST's are about half the value of their PMOST counterparts. Various BGR circuits featuring DTMOST's were successfully implemented in 0.35µm CMOS technology by engineers from University of Twente in the Netherlands in 1999. Slide#8. In order to design a complete bandgap reference circuit the DTMOST structures have been characterized and modelled. The current-to-voltage characteristic Id(Vgs) of the DTMOST's has been measured at various temperatures in a temperature chamber . The DTMOST structures came from an experimental submit in the 0.13µm CMOS technology. As expected, voltage across the DTMOST is conversely proportional to absolute temperature. By the approximation the line to the low temperature region the effective bandgap voltage is estimated equal to 410mV. Slide#9. In contrast to the conventional diode the DTMOST demonstrates exponential current-to-voltage relationship in a restricted region only. This case must be closely watched in the design of the complete circuit. Current through the diodes must stay within the range (0.1uA…2uA) at any operating temperature. Slide#10. In order to design complete circuit of the Bandgap Reference a Cadence compatible model is needed. The measurements have been the basis to develop a model for the DTMOST's in SPECTRE. I took a standard diode model and varied the parameters to find the best fit for the measured points. You may notice discrepancies in the fitting. Those can cause some inaccuracy in temperature compensation and means are needed to adjust the circuit. Slide#11. Complete Voltage Bandgap Reference circuit consists of the DTMOST devices, a pair of cascoded current sources and a two-stage operational amplifier. All the biases needed for operation of the circuit are generated on-chip. For the purpose to find the optimal operation point a set of resistors have been used. The nodes of the set are connected to the bond pads. By means of jumpers a proper value of the resistor will be chosen . The main specifications of the circuit taken from SPECTRE simulations are listed here: Abstract. A CMOS bandgap reference circuit, featuring dynamic-threshold MOS transistors (DTMOST's) has been developed in the 0.13um CMOS technology. Insensitive to temperature and power supply variations this cell is going to be a key component for high quality A/D and D/A converters. The proposed circuit fits well into the low supplyvoltage range of the current and future deep sub-micron technologies. We have carried out pre-design characterizations of the DTMOST structures taken from an experimental submit. Design and specifications of the bandgap voltage reference circuit is presented. The circuit was submitted in CuTe2 MPW submit in May 2004.