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Instruction sets
Computer architecture taxonomy.
Assembly language.
ARM processor PDA’s, video games, telephones
SHARC  DSP
© 2000 Morgan
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von Neumann architecture
Memory holds data, instructions.
Central processing unit (CPU) fetches
instructions from memory.
Separate CPU and memory distinguishes
programmable computer.
CPU registers help out: program counter
(PC), instruction register (IR), generalpurpose registers, etc.
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CPU registers
Program counter (PC):
 bit-width represents processor’s address size
 address size M  address space =?
 PC holds next instruction
 Instruction Register (IR):
 holds fetched instruction
Other registers serve as processor’s shortterm memory (index register, accumulator,
status register, …)  fast access time compared to external
memory
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CPU + memory
Address bus
200
ADD r5,r1,r3
200
PC
Data bus
CPU
Memory
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ADD IR
r5,r1,r3
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Program
Counter
Harvard architecture
address
data memory
data
address
program memory
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data
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PC
CPU
Points to
Program
memoryNot data
memory
von Neumann vs. Harvard
Harvard allows two simultaneous memory
fetches: DATA & PROGRAM
Most DSPs use Harvard architecture for
streaming data:
greater memory bandwidth;
Data and program do not compete for the
same port
(Telephone calls  speech processing  DSP)
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RISC vs. CISC
Early computers: Complex instruction set
computer (CISC):
many addressing modes;
many operations, e.g., string search, division, block transfer, …
Reduced instruction set computer (RISC):
load/store;
pipelinable instructions.
 Question: Any advantage of using RISC vs
CISC?
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Instruction set
characteristics
Fixed vs. variable length instructions.
Addressing modes: Immediate, register
addressing (direct: for regular variables, indirect: to
implement pointers), implicit addressing (accumulator),
relative, …
Number of operands.
Types of operands.
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Programming model
Programming model: Set of registers
visible to the programmer and available
for use.
Some registers are not visible (IR).
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Selecting a processor:
Achieve a desired speed with certain
power/cost requirements
Clock speed
 Number of instructions per clock cycle is different among
processors
Instructions per second (MIPS)
 Complexity of instructions may be different (for the same
function one my require less instructions)
Dhrystone benchmark: C program to exercise
processor’s integer arithmetic and string handling speed
 VAX 11/780 executes 1757 Dhrystones/sec (1MIPS machine)
 Number of Dhrystones/sec is compiler dependent
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Assembly language:
Textual description  Binary representation
Basic features:
One instruction per line.
Labels provide names for addresses (usually
in first column).
Instructions often start in later columns.
Columns run to end of line.
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ARM assembly language
example
label1 ADR
LDR
Address or
ADR
memory
location
LDR
SUB
r4,c
r0,[r4] ; a comment
r4,d
r1,[r4]
r0,r0,r1 ; comment
[c] – [d]
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SHARC assembly language
Algebraic notation terminated by
semicolon:
DAG1 and DAG2
registers
R1=DM(M0,I0), R2=PM(M8,I8);!comment
label:
R3=R1+R2;
data memory access
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program memory access
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Pseudo-ops
Some assembler directives don’t
correspond directly to instructions:
Define current address.
Reserve storage.
Constants.
NEXT
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Kaufman
ARM assembly
language
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