Download Z-PACK HS3 10 Row ELECTRICAL PERFORMANCE REPORT Literature Number 1308506

ELECTRICAL PERFORMANCE REPORT
Z-PACK HS3 10 Row
Vertical Plug to Right Angle Receptacle
Literature Number 1308506
Issued September, 2000
Copyright, Tyco Electronics Corporation
All Rights reserved
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
TABLE OF CONTENTS
INTRODUCTION.................................................................................................................................iii
What is an EPR?................................................................................................................................iii
Why use this EPR? ............................................................................................................................iii
HOW TO USE AN EPR ....................................................................................................................... iv
The Simulation Page........................................................................................................................... v
Simulation Graphs .............................................................................................................................. v
Input Voltage .................................................................................................................................. v
Near & Far End Noise Values ......................................................................................................vii
MODEL OVERVIEW ........................................................................................................................viii
The Single Line Model (SLM) ........................................................................................................viii
The Multi Line Model (MLM)........................................................................................................viii
SIMULATION DATA ........................................................................................................................... 1
Z-PACK HS3 10 Row ........................................................................................................................ 1
HS3, 10 Row, Vertical Plug to Right Angle Receptacle Electrical Interconnection Performance
Information ......................................................................................................................................... 2
MODEL WIRING PATTERNS............................................................................................................. 3
SIMULATION LOOK-UP TABLE....................................................................................................... 4
Specifications subject to change.
Consult AMP for latest design specifications.
 Copyright 2000 by AMP Incorporated
All Rights Reserved.
AMP is a registered trademark.
ii
Contents Printed on Recycled Paper
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
INTRODUCTION
The first several pages of this Electrical Performance Report (EPR) are intended to give an overview
of the AMP EPR. By understanding how to apply information from an AMP EPR, system designers
will be able to select the best AMP product for their application.
What is an EPR?
EPRs (Electrical Performance Reports) are technical documents composed of electrical simulations
of connector models. Each of these simulations varies in several system parameters. EPRs are used
to assist system design engineers in the selection of potential connector solutions for their particular
application. While there are several non-technical issues that enter into the connector selection
decision, these electrical performance criteria are becoming very important.
Why use this EPR?
The EPR provides system designers with fundamental data relating to the electrical performance of a
connector. This data, in turn, allows the system designer to decide if the connector under analysis is
the proper interconnection device for his or her application. Criteria that impact the electrical
performance of a connector include wiring patterns, edge rates, system impedances and logic
families. The EPR permutes these criteria one step at a time, while holding all other parameters
constant. This approach reveals the effects that each change may or may not cause. If used properly,
an EPR can facilitate in choosing the proper connector for an application. Furthermore, the EPR can
help in selecting wiring patterns, edge rates, system impedances, and logic families within an
application.
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
iii
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
HOW TO USE AN EPR
Following a systematic method, pertinent information can be derived from the various EPR
simulations. The parametric nature of simulations can best be explained by recognizing that various
factors affect coupled noise:
•
•
•
•
•
•
Wiring Pattern
Logic Family (excitation)
System Impedance (Zo)
Signal Risetime
Voltage Swing
Connection Capacitance
SIMULATION LOOK-UP TABLE
Consolidates all simulations in the
EPR to quickly find pertinent
simulation(s).
SIMULATION LEGEND AND NOTES
Defines Simulation Look-up Table
fields. Can include graphics to
relate.
MODEL PATTERNS
Wiring patterns used for the
simulations. Single-ended and
differential patterns are simulated,
where applicable.
Select a representative model pattern that is similar to your application setup. Find the rows in the
Simulation Look-Up Table that correspond to this wiring (model) pattern. In the table, you will see
several parameters that vary given this model pattern. Note the simulation filename of interest, and
go to that page to find graphs of electrical simulation data.
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
iv
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
The Simulation Page
The simulation page shows the graphical results of a simulation on a connector under defined system
parameters. Referring to the figure below, it can be seen that the several parameters that effect the
electro-dynamics of the connector are shown.
MODEL PATTERN
Shows the connections to
the connector model.
SIMULATION GRAPHS
Provide voltage versus time
information. Graphs include
Input Voltage, Near and Far
End Noise Voltages.
MODEL PATTERN
LEGEND
Defines connections to the
connector model.
SIMULATION
Defines logic family, voltage
swing, and rise time used in
this simulation.
INTERCONNECTION
Shows the simulation's
system impedance, and the
PAD (in the case of SMT)
or plated through-hole
capacitance.
Simulation Graphs
The value of the EPR is realized when voltage values are found on the simulation graphs. The plots
of voltage versus time reveal both absolute values of voltage levels and where they occur in time.
These values can help in determining the contribution or impact of the connector/connection on the
system noise budget. In some occurrences, where multiple lines are monitored, a rough estimate of
skew can be determined. The total noise tolerance should be determined, understanding that it is
different for different logic families.
Input Voltage
The Input Voltage graph shows the incident and far end voltage of the connector including the
connection effects (PAD or plated through hole capacitance). Overall symmetry (in the case of
differential signals) can be seen. Refer to the following graph for more information:
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
v
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
INPUT voltage graphs. In this case, a differential system, the INPUT voltages (VIA3
& VIA4) are plotted with the output voltages (VOA3 & VOA4) versus time.
Input Voltage [94103187]
VIA3
VIA4
VOA3
VOA4
2.4
VOA4 (Output voltage, pin A4)
2.2
VIA3 (Input voltage, pin A3)
2.0
VOLTAGE(mv)
1.8
1.6
1.4
1.2
VOA3 (Output voltage, pin A3)
1.0
0.8
VIA4 (Input voltage, pin A4)
0.6
0.4
0.0
0.4
0.8
1.2
1.6
2.0
TIME(ns)
The voltage response (refer to the voltage swing in following figure) of the connector should
approach that of the logic family as defined in the simulation area of the EPR graph pages. The
propagation delay of the connector can be determined as the difference in time that the incident and
far end graphs cross the same voltage level. In the case below, the propagation delay would be:
propagation delay: ∆ t = t 2
−
t1
Input Voltage [94103187]
VIA3
VIA4
VOA3
VOA4
2.4
2.2
VIA3 (Input voltage, pin A3)
2.0
VOLTAGE(mv)
1.8
1.6
1.4
Voltage Swing
1.2
VOA3 (Output voltage, pin A3)
1.0
0.8
0.6
0.4
0.0
0.4
0.8
1.2
1.6
TIME(ns)
Propagation delay of
connector
t1 t2
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
vi
2.0
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
Near & Far End Noise Values
Near and far end noise values include the effects of the return path in their determination. Simulated
values are absolute and can be included in their percent contribution to the total noise budget as
determined by the system designer. In the following Near End Noise Voltage figure, the effects of
adjacent pairs that are out-of-phase can be seen (the +/- of two differentially driven lines). Note that
similar techniques are used with the Far End Noise voltage graphs.
NEAR END NOISE VOLTAGE
vna4b4
vnf4
60.00
vna4b4 Differential Voltage between pins a4 and b4
50.00
Voltage (mV)
40.00
30.00
vnf4 Near End Noise Voltage of pin f4
20.00
10.00
0.00
-10.00
0.00
0.20
0.40
0.60
0.80
1.00
1.20
1.40
1.60
1.80
2.00
Time(ns)
To summarize, the EPR arms the system designer with simulation information from the simulation
setups that closely match his or her design. This information can be effectively used to focus on
follow-up simulations, and it is of great aid in selecting connector and wiring pattern candidates.
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
vii
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
MODEL OVERVIEW
The Single Line Model (SLM)
The SLM is used to evaluate the effects of a single set of connector
pins. A SLM is representative of a well referenced connector. A
simulation with the SLM can show the following effects:
PROPAGATION DELAY
DRIVE POWER
ATTENUATION
TIMING
REFLECTIONS
Single Line Model
IMPEDANCE
The SLM for the connector found in this EPR is listed on the next page.
Note: A SLM was NOT used to generate simulation data in this EPR.
(FOR CROSSTALK, A MULTI-LINE MODEL MUST BE USED.)
The Multi Line Model (MLM)
The MLM (Multi-Line Model) is used in all the simulations found in
this EPR. The MLM accounts for the electrostatic and electromagnetic
coupling (crosstalk) as well as the common impedance noise found in a
connector. Its structure couples, in three dimensions, all pins to one
another. This results in a complex model that uses series resistance,
inductance, coupling capacitance and inductive coupling coefficients so
arranged to allow connections at both the input and output. This
modeling technique effectively shows coupled noise at the expense of
CPU runtime. Simulations done using the MLM will show the following
information:
PROPAGATION DELAY
DRIVE POWER
CROSSTALK
ELECTROSTATIC COUPLING
ATTENUATION
TIMING
COMMON MODE NOISE
ELECTROMAGNETIC COUPLING
Multi Line Model - The
Fundamental Structure
REFLECTIONS
IMPEDANCE
The fundamental MLM varies in the number of pins (rows & columns) and the number of sections.
Note that faster rise times require multiple sections.
To learn more about AMP Simulation capabilities,
e-mail us: [email protected]
URL: www.amp.com/simulation
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
viii
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
FVM – Footprint Via Matrix
With increasing data rates, the rise-time of the signals are becoming fast enough that the footprint of
a connector will significantly affect the electrical performance of an interconnect. While the
structure of the connector is fixed and can be readily specified for its insertion loss characteristics in
a given line environment, the connection is highly variable due to the influence of the footprint. The
approach of representing the footprint with only series capacitance may no longer suffice. A
challenge posed to the design engineer is how to better represent the connector footprint in a system
simulation. One practical approach is to use a Footprint Via Matrix (FVM) Model.
The structure of the FVM model is similar to that of the connector’s matrix model; containing series
Resistance and Inductance, along with inter-via mutual capacitance and inductance matrices. The
inter-via matrices represent the coupling between plated through holes. In addition, the FVM model
structure includes a via-to-plane capacitance matrix. The via-to-plane capacitance matrix represents
the coupling between each plated through hole and its adjacent planes and traces.
The FVM model values are a function of the following:
(1)
(2)
(3)
(4)
(5)
PCB thickness (length)
PCB material (Dielectric Constant and Dissipation Factor)
Pad and anti-pad dimensions
Stack-up (number of planes and spacing)
Trace connection location
(a) a high-connected signal trace (via in full stub configuration; presenting maximum low
impedance condition)
(b) a mid-connected signal trace (via in half-stub, half series configuration)
(c) a low-connected signal trace (via in full series configuration; presenting minimum low
impedance condition)
NOTE : THE FOOTPRINT VIA MATRIX MODEL IS A PRACTICAL ENGINEERING
TOOL COVERING A GENERIC PCB SPECIFICATION. YOUR PARTICULAR BOARD
STACKUP MAY OR MAY NOT BE FAITHFULLY MODELED BY THE EXAMPLE
MODEL.
Via-to-Plane Structure
(Side View of VIA)
Inter-VIA Structure
Top-Connected Trace
GND
GND
Mid-Connected Trace
GND
GND
Bottom-Connected Trace
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
ix
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
SIMULATION DATA
Z-PACK HS3 10 Row
Vertical Plug to Right Angle Receptacle
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
1
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
HS3, 10 Row, Vertical Plug to Right Angle
Receptacle Electrical Interconnection
Performance Information
a
This document contains abstracts of the results
of various computer simulations of electrical
interconnection performance.
The HS3 10 Row connector evaluated in this
report is an impedance controlled board to board
connector that is ideal for high-end server, mass
storage, and networking applications.
A BC DE FG HJ K
gr1 gr2 gr3 gr4 gr5
The Model Pattern Orientation in this set of data
represents a board to board interconnection. The
simulations are run on the three column model,
as shown in Section a-a, which is adequate for
most wiring patterns.
a
Model Pattern Orientation (Section a-a)
As shown in the “Simulation Circuit Abstract”
figure to the right, the simulation model is a
validated matrix circuit model (AMP MLM
P/N MLM -1999-3681-066) which provides for
the series resistance and inductance elements of
each line, the electrostatic coupling between
lines, and the electromagnetic coupling between
lines. The model for this connector has multiple
sections and is useful for digital signals with
edge rates as fast as 125 ps.
CONNECTOR MODEL
RC
driven line(s)
RS
VS
LC
CP
CP
near end ref
far end ref
RC
reference line(s)
RT
LC
C
M
CP
quiet line(s)
RC
L
M
CP
RT
LC
Simulation Circuit Abstract
The model is configured so that any position in
the matrix may be assigned as a driven line, a
quiet line, or a reference line. Each line can be
terminated (RT) as desired, pad capacitances
(CP) can be assigned as desired, with driving
functions (VS) and source impedances (RS)
assigned as desired. The near end and far end
references are isolated to allow observation of
common impedance effects of the connector.
signal
coupled region
Vs
Vb
Vf
Backward
crosstalk
Forward
crosstalk
Electrostatic and Electromagnetic Crosstalk
signal
The simulation model outputs include both the
electrostatic (E) and magnetic (M) crosstalk and
the common mode noise contributions. This
sum is reported as Near End Noise Voltage
and/or Far End Noise Voltage.
driven line
i
(-)
(+)
Zc
(-)
(+)
noise
(+)
(-)
Common Impedance Noise
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
RT
2
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
MODEL WIRING PATTERNS
1
-
All Signal
All Signal
(Single Ended)
(Differential Vertical)
-
2
-
a
K
X
gr5
-
3
-
Q
X
-
a
X
1
-
-
2
2:1 Single Ended
-
-
a
K
1
-
a
X
I
-
Q
X
gr5
3
X
gr5
I
J
H
J
a
a
a
J
a
Q
a
H
a
a
a
H
a
A
a
X
gr4
X
X
G
a
A
a
F
a
a
a
X
gr3
X
X
gr4
X
X
X
gr4
G
aI
AI
aI
F
a
Q
a
X
gr3
X
X
-
-
2
-
a
K
X
-
X
X
-
-
a
X
X
a
X
3
Q
X
a
X
a
X
G
X
X
X
F
a
A
a
gr3
X
X
X
E
a
Q
a
E
aI
Q
aI
E
X
X
X
D
a
a
a
D
a
a
a
D
a
a
a
X
gr2
X
X
a
a
a
C
B
a
a
a
B
X
gr1
X
X
a
A
X
gr2
C
a
X
X
X
X
a
a
a
I
C
X
X
X
a
Q
a
B
a
a
a
X
X
I
A
gr2
I
X
gr1
Q
X
I
gr1
Q
a
a
I
X
X
a
A
X
Q
a
2:1 Differential Vertical
4:1 Differential Vertical
(Ground towards Inside)
(Ground Towards Outside)
1
-
-
2
-
-
3
-
1
a
K
a
Q
X
J
H
gr4
X
X
gr5
aI
Q
aI
X
X
X
X
X
X
-
X
-
-
a
H
I
-
-
X
X
a
X
3
X
X
J
gr4
2
X
K
gr5
-
Q
a
Q
I
X
a
X
X
G
X
X
X
G
a
a
a
F
a
A
a
F
aI
aI
aI
gr3
X
X
I
E
a
D
X
gr2
X
X
I
gr3
A
a
X
X
X
X
I
X
X
A
a
A I Monitored Active (Inverted) Line
D
aI
AI
aI
q Passive Line
gr2
X
X
X
Q Monitored Passive Line
X
C
a
Q
a
B
a
Q
a
B
aI
Q
aI
A
X
a
X
Q
gr1
a
I
A Monitored Active (Driven) Line
a
X
I
a Active (Driven) Line
E
X
X
Ground Line
aI Active (Inverted) Line
X
C
gr1
LEGEND
A
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
X
X
X
X
X
3
X
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
SIMULATION LOOK-UP TABLE
(Indexed by S/G Ratio, then by Logic Family, then by Tr)
Table Legend:
Cp
DH
DV
GI
GO
Logic:
S/G Ratio
Tr
Vf
Vo
VMM
Zo:
Pad or Plated Through Hole capacitance
Differential signal (horizontal pairs)
Differential signal (vertical pairs)
Grounded Lines Towards Inside Rows
Grounded Lines Towards Outside Rows
Logic family simulated
Ratio of signal lines to reference (ground) lines
Rise time of source
Source final voltage
Source initial voltage
Via Matrix Model
Characteristic Impedance
Multi-Line Model Used: HSC 10319.AIS (Connector)
HFP32MM (Footprint) - Daughtercard
FP2_LH_M (Footprint) – Backplane
Simulation Tool: HSPICE v99.2
Simulation
Filename
Page
2000092101
2000092102
2000092103
2000092104
2000092105
2000092106
2000092107
2000092108
2000092109
2000092110
5
6
7
8
9
10
11
12
13
14
S/G
Ratio
Driver
Type(1)
Tr
Vo
Vf
Zo
(ns) (Volts) (Volts) (Ohms)
All Signal
CMOS
0.5
All Signal
CMOS
1.0
DV
All Signal
PECL
0.3
All SignalDV Fibre-channel 0.15
2:1
CMOS
0.5
2:1
CMOS
1.0
2:1DV;GI
PECL
0.3
2:1DV;GI Fibre-channel 0.15
4:1DV;GO
PECL
0.3
4:1DV;GO Fibre-channel 0.15
0.0
0.0
1.5
1.8
0.0
0.0
1.5
1.8
1.5
1.8
3.3
3.3
2.4
2.5
3.3
3.3
2.4
2.5
2.4
2.5
65
65
50
50
65
65
50
50
50
50
Cp
(pf)
FVM(2)
FVM
FVM
FVM
FVM
FVM
FVM
FVM
FVM
FVM
(1) DRIVER TYPE:
Piece-wise linear voltage sources are used to simulate the drivers. The PWL
sources are developed based on voltage swing and rise time (the dv/dt values are linear between the
10%-90% or 20%-80% points, depending on the logic’s specification).
(2) FVM (Footprint Via Matrix – reference page ix): The FVM used for all simulations herein
represents vias with mid-connected traces)for a .200” thick backplane and .100” thick load card.
Plane spacing was designed to maintain 50 ohm stripline traces using 8 mil trace widths in FR4
material. 0.052” diameter circular antipads were included in the modeling.
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
4
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
2000092101
SIMULATION FILENAME:
MODEL PATTERN
INPUT VOLTAGE
vig2
All Signal
vog2
(Single Ended)
1
0.0
0.2
0.4
0.6
0.8
1.0
-
1.2
1.4
1.6
1.8
2.0
3.50
gr5
3.00
X
X
a
a
X
X
Voltage (V)
a
A
F
a
a
X
a
Q
D
a
a
X
X
a
a
B
a
a
X
X
a
A
a
a
a
a
a
a
X
C
gr1
-
a
X
E
gr2
-
X
G
X
3
X
H
1.00
0.00
-
Q
a
gr3
0.50
-
a
2.50
1.50
2
J
gr4
2.00
-
a
K
Time (ns)
a
a
X
Q
a
-0.50
NEAR END NOISE VOLTAGE
vne2
vna2
LEGEND
vnk2
X
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
200.00
a Active (Driven) Line
180.00
A Monitored Active (Driven) Line
160.00
aI Active (Inverted) Line
140.00
Voltage (mV)
Ground Line
A I Monitored Active (Inverted) Line
120.00
q Passive Line
100.00
Q Monitored Passive Line
80.00
60.00
DRIVER TYP
40.00
20.00
∆ 0.0
0.00
CMOS
V to 3.3
V
PWL Ramp
NEAR END NOISE VOLTAGE
vfa2
vfe2
Tr (ns): 0.5 (20%-80%)
vfk2
INTERCONNECTION
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
50.00
1.8
2.0
65 Ohm Lines
FVM* used for Cp
40.00
30.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
20.00
Voltage (mV)
1.6
10.00
GRAPH NOTES
0.00
-10.00
VI - Input Voltage
VO - Output Voltage
-20.00
-30.00
VN - Near End Noise Voltage
-40.00
VF - Far End Noise Voltage
-50.00
PWL - Piece Wise Linear
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 5
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
MODEL PATTERN
EPR 1308506
Issued: 09-2000
2000092102
SIMULATION FILENAME:
INPUT VOLTAGE
All Signal
vig2
(Single Ended)
1
-
-
2
-
a
K
gr5
X
-
X
a
a
H
a
a
X
-
-
a
Time (ns)
0.0
X
J
gr4
3
Q
X
vog2
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3.50
a
3.00
a
X
2.50
a
F
gr3
X
X
gr1
X
a
0.50
a
0.00
X
Q
a
-0.50
LEGEND
X
1.50
1.00
a
a
X
a
2.00
X
a
a
B
a
a
X
a
C
a
X
Q
a
D
gr2
a
a
X
a
E
A
A
Voltage (V)
a
G
NEAR END NOISE VOLTAGE
vnk2
Ground Line
vne2
vna2
Time (ns)
0.0
a Active (Driven) Line
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
120.00
A Monitored Active (Driven) Line
100.00
aI Active (Inverted) Line
80.00
q Passive Line
Q Monitored Passive Line
Voltage (mV)
AI Monitored Active (Inverted) Line
60.00
40.00
20.00
DRIVER TYPE:
CMOS
0.00
∆ 0.0 V to 3.3 V
-20.00
PWL Ramp
FAR END NOISE VOLTAGE
vfa2
vfe2
vfk2
Tr (ns): 1.0 (10%-90%)
Time (ns)
INTERCONNECTION
0.0
0.5
1.0
20.00
65 Ohm Lines
15.00
FVM* used for Cp
10.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
VI - Input Voltage
VO - Output Voltage
Voltage (mV)
GRAPH NOTES
5.00
0.00
-5.00
-10.00
VN - Near End Noise Voltage
VF - Far End Noise Voltage
PWL - Piece Wise Linear
-15.00
-20.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 6
1.5
2.0
2.5
3.0
3.5
4.0
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
SIMULATION FILENAME:
EPR 1308506
Issued: 09-2000
2000092103
INPUT VOLTAGE
vih2
MODEL PATTERN
voh2
vig2
All Signal
vog2
(Differential Vertical)
1
0.0
0.2
0.4
0.6
0.8
1.0
1.2
gr5
2.40
X
-
a
X
aI
a
A
a
X
X
I
I
A
a
X
X
I
a
a
Q
X
a
X
E
a
I
Q
a
D
a
a
a
X
X
I
C
X
X
a
Q
X
I
A
I
a
a
gr1
I
I
a
B
1.20
-
H
gr2
1.40
3
X
F
1.60
-
Q
Q
gr3
1.80
-
aI
G
2.00
2
J
gr4
2.20
-
a
2.60
Voltage (V)
-
K
Time (ns)
a
X
I
Q
a
a
1.00
NEAR END NOISE VOLTAGE
vnk2j2
vnf2e2
LEGEND
vnb2a2
X
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
10.00
a Active (Driven) Line
A Monitored Active (Driven) Line
0.00
aI Active (Inverted) Line
-10.00
A I Monitored Active (Inverted) Line
-20.00
Voltage (mV)
Ground Line
q Passive Line
-30.00
Q Monitored Passive Line
-40.00
-50.00
DRIVER TYP
PECL
-60.00
∆ 1.5
-70.00
V to 2.4
V
PWL Ramp
FAR END NOISE VOLTAGE
vfb2a2
vff2e2
Tr (ns): 0.3 (20%-80%)
vfk2j2
INTERCONNECTION
Time (ns)
0.0
0.2
0.4
0.6
0.8
20.00
1.0
1.2
50 Ohm Lines
FVM* used for Cp
15.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
Voltage (mV)
10.00
GRAPH NOTES
5.00
VI - Input Voltage
VO - Output Voltage
0.00
VN - Near End Noise Voltage
-5.00
VF - Far End Noise Voltage
PWL - Piece Wise Linear
-10.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 7
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
MODEL PATTERN
EPR 1308506
Issued: 09-2000
2000092104
SIMULATION FILENAME:
INPUT VOLTAGE
All Signal
vih2
vig2
(Differential Vertical)
gr5
-
-
2
-
a
X
-
3
-
Q
X
-
a
I
a
Q
a
H
a
A
a
X
I
G
I
E
D
gr2
X
gr1
A
1.0
1.80
a
1.20
I
a
1.00
LEGEND
X
0.9
1.40
X
Q
a
0.8
1.60
a
Q
X
I
0.7
2.00
I
a
a
X
0.6
X
I
a
B
I
a
a
a
I
C
a
X
X
0.5
2.20
I
Q
a
a
0.4
a
Q
X
0.3
2.40
X
A
a
X
0.2
I
I
a
F
gr3
X
0.1
2.60
J
gr4
Tim e (ns)
0.0
X
Voltage (V)
1
K
voh2
vog2
NEAR END NOISE VOLTAGE
vnb2a2
Ground Line
vnf2e2
vnk2j2
T im e (ns)
0.0
a Active (Driven) Line
A Monitored Active (Driven) Line
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
-10.00
AI Monitored Active (Inverted) Line
-20.00
Voltage (mV)
Q Monitored Passive Line
0.2
0.00
aI Active (Inverted) Line
q Passive Line
0.1
10.00
-30.00
-40.00
-50.00
DRIVER TYPE:
-60.00
Fibre-channel
-70.00
∆ 1.8 V to 2.5 V
-80.00
PWL Ramp
FAR END NOISE VOLTAGE
vfb2a2
vff2e2
vfk2j2
Tr (ns): 0.15 (10%-90%)
Time (ns)
INTERCONNECTION
0.0
0.1
0.2
0.3
35.00
50 Ohm Lines
30.00
FVM* used for Cp
25.00
20.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
VI - Input Voltage
VO - Output Voltage
VN - Near End Noise Voltage
VF - Far End Noise Voltage
PWL - Piece Wise Linear
Voltage (mV)
GRAPH NOTES
15.00
10.00
5.00
0.00
-5.00
-10.00
-15.00
-20.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 8
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
EPR 1308506
Issued: 09-2000
2000092105
SIMULATION FILENAME:
MODEL PATTERN
INPUT VOLTAGE
vif2
2:1 Single Ended
vof2
1
0.0
0.2
0.4
0.6
0.8
1.0
-
1.2
1.4
1.6
1.8
2.0
3.50
gr5
3.00
X
X
a
a
X
X
Voltage (V)
X
X
F
a
A
X
X
X
D
a
a
X
X
X
X
B
a
a
X
X
a
X
a
X
a
X
a
X
Q
a
A
X
X
C
gr1
-
a
X
E
gr2
-
X
G
X
3
X
H
1.00
0.00
-
Q
X
gr3
0.50
-
X
2.50
1.50
2
J
gr4
2.00
-
a
K
Time (ns)
a
-0.50
NEAR END NOISE VOLTAGE
vna2
LEGEND
vnk2
X
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
100.00
Ground Line
a Active (Driven) Line
A Monitored Active (Driven) Line
80.00
aI Active (Inverted) Line
A I Monitored Active (Inverted) Line
Voltage (mV)
60.00
q Passive Line
40.00
Q Monitored Passive Line
20.00
DRIVER TYP
0.00
∆ 0.0
-20.00
CMOS
V to 3.3
V
PWL Ramp
FAR END NOISE VOLTAGE
vfa2
Tr (ns): 0.5 (20%-80%)
vfk2
INTERCONNECTION
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
30.00
1.6
1.8
2.0
65 Ohm Lines
FVM* used for Cp
20.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
Voltage (mV)
10.00
GRAPH NOTES
0.00
VI - Input Voltage
VO - Output Voltage
-10.00
VN - Near End Noise Voltage
-20.00
VF - Far End Noise Voltage
PWL - Piece Wise Linear
-30.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 9
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
MODEL PATTERN
1
-
-
2
-
INPUT VOLTAGE
-
gr5
X
X
X
X
H
a
a
X
-
X
vif2
vof2
-
a
Time (ns)
0.0
X
J
gr4
3
Q
a
2000092106
SIMULATION FILENAME:
2:1 Single Ended
K
EPR 1308506
Issued: 09-2000
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
3.50
X
3.00
a
X
2.50
X
A
a
F
gr3
X
X
X
E
a
X
X
a
D
X
X
a
2.00
Voltage (V)
X
G
1.50
a
1.00
gr2
X
X
X
C
X
X
X
B
a
a
a
gr1
A
X
X
0.00
X
Q
a
0.50
a
-0.50
LEGEND
X
NEAR END NOISE VOLTAGE
vnk2
Ground Line
vna2
Time (ns)
0.0
a Active (Driven) Line
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
60.00
A Monitored Active (Driven) Line
50.00
aI Active (Inverted) Line
40.00
q Passive Line
Q Monitored Passive Line
Voltage (mV)
AI Monitored Active (Inverted) Line
30.00
20.00
10.00
DRIVER TYPE:
CMOS
0.00
∆ 0.0 V to 3.3 V
-10.00
PWL Ramp
FAR END NOISE VOLTAGE
vfa2
vfk2
Tr (ns): 1.0 (10%-90%)
Time (ns)
INTERCONNECTION
0.0
0.5
1.0
15.00
65 Ohm Lines
FVM* used for Cp
10.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
Voltage (mV)
GRAPH NOTES
5.00
0.00
VI - Input Voltage
-5.00
VO - Output Voltage
VN - Near End Noise Voltage
-10.00
VF - Far End Noise Voltage
PWL - Piece Wise Linear
-15.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 10
1.5
2.0
2.5
3.0
3.5
4.0
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
SIMULATION FILENAME:
EPR 1308506
Issued: 09-2000
2000092107
INPUT VOLTAGE
MODEL PATTERN
vif2
vie2
2:1 Differential Vertical
vof2
voe2
(Groun d towards Inside)
1
0.2
0.4
0.6
0.8
1.0
1.2
2.60
gr5
2.40
Voltage (V)
2.00
3
-
X
-
a
X
aI
H
X
X
X
X
X
X
G
X
X
F
a
A
X
X
X
a
X
E
aI
AI
aI
D
X
X
X
gr2
1.20
X
-
Q
Q
1.60
1.40
-
aI
gr3
1.80
2
J
gr4
2.20
-
a
K
Time (ns)
0.0
-
X
X
X
C
X
X
B
a
Q
gr1
X
X
aI
A
X
a
X
aI
Q
1.00
NEAR END NOISE VOLTAGE
vnb2a2
LEGEND
vnk2j2
X
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
25.00
Ground Line
a Active (Driven) Line
A Monitored Active (Driven) Line
20.00
aI Active (Inverted) Line
A I Monitored Active (Inverted) Line
Voltage (mV)
15.00
q Passive Line
10.00
Q Monitored Passive Line
5.00
DRIVER TYP
0.00
∆ 1.5
-5.00
PECEL
V to 2.4
V
PWL Ramp
FAR END NOISE VOLTAGE
vfb2a2
Tr (ns): 0.3 (10%-90%)
vfk2j2
INTERCONNECTION
Time (ns)
0.0
0.2
0.4
0.6
0.8
4.00
1.2
50 Ohm Lines
FVM* used for Cp
2.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
0.00
-2.00
Voltage (mV)
1.0
-4.00
GRAPH NOTES
-6.00
VI - Input Voltage
VO - Output Voltage
-8.00
-10.00
VN - Near End Noise Voltage
-12.00
VF - Far End Noise Voltage
-14.00
PWL - Piece Wise Linear
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 11
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
MODEL PATTERN
EPR 1308506
Issued: 09-2000
2000092108
SIMULATION FILENAME:
INPUT VOLTAGE
2:1 Differential Vertical
vif2
vie2
(Groun d towards Inside)
1
-
-
2
-
gr5
X
X
-
-
a
Time (ns)
0.0
X
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.60
aI
Q
X
H
gr4
3
X
aI
J
-
Q
a
K
vof2
voe2
X
2.40
X
X
X
2.20
X
A
a
F
gr3
X
gr2
X
X
AI
X
D
a
X
aI
E
X
aI
X
X
X
X
X
X
B
a
Q
a
A
X
X
a
I
1.80
1.60
X
C
gr1
2.00
Voltage (V)
X
G
1.40
1.20
X
I
Q
a
1.00
LEGEND
X
NEAR END NOISE VOLTAGE
Ground Line
vnb2a2
vnk2j2
T im e (ns)
0.0
a Active (Driven) Line
35.00
A Monitored Active (Driven) Line
30.00
aI Active (Inverted) Line
25.00
AI Monitored Active (Inverted) Line
Q Monitored Passive Line
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
20.00
Voltage (mV)
q Passive Line
0.1
15.00
10.00
5.00
DRIVER TYPE:
0.00
Fibre-channel
-5.00
∆ 1.8 V to 2.5 V
-10.00
PWL Ramp
FAR END NOISE VOLTAGE
vfb2a2
vfk2j2
Tr (ns): 0.15 (10%-90%)
Time (ns)
INTERCONNECTION
0.0
0.1
0.2
0.3
15.00
50 Ohm Lines
10.00
FVM* used for Cp
5.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
VI - Input Voltage
VO - Output Voltage
VN - Near End Noise Voltage
VF - Far End Noise Voltage
PWL - Piece Wise Linear
Voltage (mV)
GRAPH NOTES
0.00
-5.00
-10.00
-15.00
-20.00
-25.00
-30.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 12
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
SIMULATION FILENAME:
EPR 1308506
Issued: 09-2000
2000092109
INPUT VOLTAGE
MODEL PATTERN
vie2
vid2
4:1 Differential Vertical
voe2
vod2
(Ground Towards Outside)
1
0.2
0.4
0.6
0.8
1.0
1.2
2.60
gr5
2.40
X
X
aI
Q
X
Voltage (V)
3
-
-
X
X
H
X
a
aI
X
G
a
a
a
F
aI
aI
aI
X
X
X
E
a
A
D
aI
AI
1.60
gr2
1.20
-
X
Q
gr3
1.40
-
a
2.20
1.80
2
J
gr4
2.00
-
X
K
Time (ns)
0.0
-
X
X
a
aI
X
C
a
Q
a
B
a
I
Q
a
gr1
X
X
X
A
I
X
X
X
1.00
NEAR END NOISE VOLTAGE
vnc2b2
LEGEND
vnj2h2
X
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
5.00
Ground Line
a Active (Driven) Line
A Monitored Active (Driven) Line
0.00
aI Active (Inverted) Line
A I Monitored Active (Inverted) Line
Voltage (mV)
-5.00
q Passive Line
-10.00
Q Monitored Passive Line
-15.00
DRIVER TYP
-20.00
∆ 1.5
-25.00
PECL
V to 2.4
V
PWL Ramp
FAR END NOISE VOLTAGE
vfc2b2
Tr (ns): 0.3 (20%-80%)
vfj2h2
INTERCONNECTION
Time (ns)
0.0
0.2
0.4
0.6
0.8
1.0
6.00
1.2
50 Ohm Lines
FVM* used for Cp
4.00
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
Voltage (mV)
2.00
GRAPH NOTES
0.00
VI - Input Voltage
VO - Output Voltage
-2.00
VN - Near End Noise Voltage
-4.00
VF - Far End Noise Voltage
PWL - Piece Wise Linear
-6.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 13
Electrical Performance Report – Z-PACK HS3, 10 Row,
Vertical Plug to Right Angle Receptacle
MODEL PATTERN
EPR 1308506
Issued: 09-2000
2000092110
SIMULATION FILENAME:
INPUT VOLTAGE
4:1 Differential Vertical
voe2
(Ground Towards Outside)
1
-
-
2
-
X
K
gr5
X
-
X
vid2
vod2
-
Time (ns)
0.0
X
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
2.60
a
Q
aI
H
gr4
-
X
X
a
J
3
X
vie2
2.40
aI
Q
X
X
2.20
G
a
a
a
F
I
I
I
X
a
a
X
X
E
a
A
a
D
I
I
I
a
gr2
X
A
a
X
a
Q
a
B
a
I
Q
a
A
X
1.60
1.40
I
X
X
1.20
X
X
X
1.00
LEGEND
X
1.80
X
C
gr1
2.00
Voltage (V)
a
gr3
NEAR END NOISE VOLTAGE
vnc2b2
Ground Line
vnj2h2
T im e (ns)
0.0
a Active (Driven) Line
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
5.00
A Monitored Active (Driven) Line
0.00
aI Active (Inverted) Line
-5.00
q Passive Line
Q Monitored Passive Line
Voltage (mV)
AI Monitored Active (Inverted) Line
-10.00
-15.00
-20.00
DRIVER TYPE:
Fibre-channel
-25.00
∆ 1.8 V to 2.5 V
-30.00
PWL Ramp
FAR END NOISE VOLTAGE
vfc2b2
vfj2h2
Tr (ns): 0.15 (10%-90%)
INTERCONNECTION
Time (ns)
0.0
0.1
0.2
0.3
15.00
50 Ohm Lines
FVM* used for Cp
10.00
GRAPH NOTES
VI - Input Voltage
VO - Output Voltage
VN - Near End Noise Voltage
VF - Far End Noise Voltage
PWL - Piece Wise Linear
Voltage (mV)
* NOTE: FVM=Footprint Via Matrix
(reference page ix)
5.00
0.00
-5.00
-10.00
For drawings, technical data, or samples, contact your AMP Sales Engineer
or call the AMP Product Information Center: 1-800-522-6752
Page 14
0.4
0.5
0.6
0.7
0.8
0.9
1.0
1308506-AMP-AMP-09/2000