Download Lecture 11

Low-power & low voltage
Interconnects in SoC
2006. 11. 01
Double peak profile in
interconnect length of VLSI chip
Why interconnect power
dominates from now
• >70% power dissipated in interconnect
and clock in 0.18 micron technology
• Situation in finer technology will be
more severe as chip size upscales and
there’s a certain percentage of long
interconnects such as clock network
• Small cap’s within each cell can be
lumped into device terminal cap’s, while
int
Interconnect modeling
• Depending on the relative magnitude of time
of flight and signal rise(fall) time(lumped,
distributed, or transmission line), frequency
(including L or not), and lossiness (including
R or not);
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–
–
–
–
Lumped C
Lumped RC
Distributed RC
Distributed LC or Transmission line
Distributed RLC or Lossy Transmission line
Due to increasing aspect ratio of metal
cross-section
wire-to-wire cap becomes more important.
Wire basics
• C=Cpp+Cfringe for a single microstrip wire
• For other wires surrounded by other wires
add Csidewall
• If there’s no surrounding wires, large
inductance may appear depending on the
return path.
• Wave velocity given by
= Co/
r
• Zo ; characteristic impedance
• Attenuation factor
= r/2Zo
• If BL>1 model as RC wire, otherwise as lossy
transmission line
Td = (Rd(Cd+Cw+CL)+Rw(Cw/2+CL))log(2)
Reflection depends on
termination in transmission line
Optimal section length ;
Divide wire of length L into m sections
Homework ; derive them.