Download H-Bridge inverter control circuit class notes

EE462L, Spring 2014
Implementation of Unipolar PWM
Modulation for H-Bridge Inverter
(pre-fall 2009 - but discrete components
provide a better sense of how this circuit
operates)
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H-Bridge Inverter Basics – Creating AC from DC
Switching rules
Either A+ or A – is closed,
but never at the same time
Either B+ or B– is closed,
but never at the same time
Vdc
A+
Va
B+
Load
A–
!
Vb
B–
Can use identical isolated firing signals
for A+, A–, with inverting and noninverting drivers to turn on, turn off
simultaneously
Same idea for B+, B–
The A+, A– firing signal is a scaled
version of Va
The B+, B– firing signal is a scaled
version of Vb
Vload  VA  VB  VAB
The difference in the two firing signals
is a scaled version of Vab
2
!
Implementation of Unipolar PWM
Vcont is the input signal we want to amplify at the output of the inverter.
Vcont is usually a sinewave, but it can also be a music signal.
Vcont
Vtri
−Vcont
The implementation rules are:
Vcont > Vtri , close switch A+, open
switch A– , so voltage Va = Vdc
Vcont < Vtri , open switch A+, close
switch A– , so voltage Va = 0
–Vcont > Vtri , close switch B+, open
switch B– , so voltage Vb = Vdc
–Vcont < Vtri , open switch B+, close
switch B– , so voltage Vb = 0
Vtri is a triangle wave whose frequency is at least 30 times greater
than Vcont.
Ratio ma = peak of control signal divided by peak of triangle wave
3
Ratio mf = frequency of triangle wave divided by frequency of control signal
!
Implementation of Unipolar PWM Modulation
for H-Bridge Inverter
Vload
Progressively
wider pulses
at the center
Progressively
(peak of
narrower pulses
sinusoid)
at the edges
Vdc
Unipolar Pulse-Width
Modulation (PWM)
−Vdc
4
The four firing circuits do not have the same ground
reference. Thus, the firing circuits require isolation.
!
Vdc
(source of power delivered to load)
A+
Local ground
reference for A+
firing circuit
Local ground
reference for B+
firing circuit
S
S
S
Load
A–
Local ground
reference for A−
firing circuit
B+
B–
S
Local ground
reference for B−
firing circuit
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6
This year’s circuit
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Output of the Comparator Chip
Comparator Gives V(A+,A–)
wrt. Common (0V)
V(A+,A–)
+12V
from DC-DC chip
1.5kΩ
+12V
1.5kΩ
–12V
270kΩ
Vtri
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1
Vcont > Vtri
Comp
5
1kΩ
Vcont
4
Vcont < Vtri
Since the comparator
compares signals that can be
either positive or negative, the
comparator must be powered
by ±V supply
Use V(A+,A–) wrt. –12V
270kΩ
Vcont > Vtri
–Vcont
+24V
–12V
from DC-DC chip
0V
Common (0V) from DC-DC chip
Vcont < Vtri
8
Comparator Gives V(B+,B–)
wrt. Common (0V)
Output of the Comparator Chip
V(B+,B–)
+12V
from DC-DC chip
–Vcont > Vtri
+12V
1.5kΩ
–12V
1.5kΩ
270kΩ
Vtri
8
1
Comp
5
1kΩ
Vcont
4
Since the comparator
compares signals that
can be either positive or
negative, the
comparator must be
powered by ±V supply
Use V(B+,B–) wrt. –12V
270kΩ
–Vcont
– Vcont < Vtri
–12V
from DC-DC chip
Common (0V) from DC-DC chip
– Vcont > Vtri
+24V
0V
– Vcont < Vtri
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This year’s circuit
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Input
Wall wart
Output
Op amps
Notes for the above converter chip – keep the input and output sections isolated from each
other.
When energizing your circuit, check the +12V and −12V outputs to make sure they are OK. Low
voltages indicate a short circuit in your wiring, which can burn out the chip in a few minutes.
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Triangle wave generator
12
Dual Op Amp
Dual Comparator
13
Indicates DC
offset
Figure 9. Output of triangle-wave generator (with respect to
protoboard common)
Equal rise and fall times
Figure 10. Rise and fall times of the triangle wave
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+4V
0V
−4V
DC offset
minimized
Save screen
snapshot #1
Figure 11. Output of high-pass filter
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+24V
0V
+24V
For ma = 0, use a
multimeter to check the
following DC voltages
with respect to –12V ref:
V(A+,A–) ≈ 11.8Vdc
V(B+,B–) ≈ 11.8Vdc
0V
Save screen
snapshot #2
Figure 12. Output control voltages V(A+,A–) and V(B+,B–), with respect to
protoboard –12V reference, with Vcont = 0 (i.e., the ma = 0 case)
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+24V
0V
+24V
0V
Save screen
snapshot #3
Figure 13. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect
to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is positive)
+24V
0V
+24V
0V
Figure 14. Output control voltage V(A+,A–) on top, and V(B+,B–) on bottom, with respect
to protoboard –12V reference, with ma > 0 (the situation shown is where Vcont is negative)
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split
+24V
0V
−24V
split
Save screen
snapshot #4
Figure 15. Idealized Vload, with ma just into the overmodulation region
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+24V
0V
−24V
Save screen
snapshot #5
Figure 16. Idealized Vload observed in the scope averaging mode, with ma in the
linear region
Flat toping indicates
the onset of
overmodulation
+24V
0V
−24V
Figure 17. Idealized Vload observed in the scope averaging mode, with ma just into
the overmodulation region
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Approaching a
square wave
+24V
0V
−24V
Figure 18. Idealized Vload observed in the scope averaging mode, with ma almost into
the saturation (i.e., square wave) region
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2ftri cluster (46kHz)
4ftri cluster
(92kHz)
60Hz
component
Figure 19. FFT of idealized Vload in the linear region with ma ≈ 1.0, where the
frequency span and center frequency are set to 100kHz and 50kHz, respectively
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