Download MOS Applications and Biasing

ECE 340
ELECTRONICS I
MOS
APPLICATIONS AND BIASING
MOSFET REGIONS OF
OPERATION
• CUT OFF
• LINEAR, OHMIC, TRIODE
• SATURATION
CUT OFF REGION OF OPERATION
vDS  vGS  VTH 
iD  0
LINEAR, OHMIC, TRIODE REGION
OF OPERATION
vDS  vGS  VTH 
W
iD  k 
L
1 2 

 vGS  VTH vDS  vDS 
2


SATURATION REGION OF
OPERATION
vDS  vGS  VTH 
1 W
iD  k 
2 L

2
vGS  VTH  1  vDS 

  0 small 
1 W
 iD  k 
2 L

2
vGS  VTH 

MOSFET CHARACTERISTICS
1.5mA
ID
1.0mA
vGS3
Linear, Ohmic,
Triode ROP
Saturation ROP
vGS2
0.5mA
vGS1
0mA
Cutoff ROP
0V
2V
4V
6V
vDS
8V
10V
12V
MOSFET BIASING
• SELECTION OF GATE TO SOURCE VOLTAGE
• PRODUCES DC DRAIN TO SOURCE VOLTAGE
• PRODUCES DC DRAIN CURRENT
• DEFINES REGION OF OPERATION
DC LOAD LINE
• INPUT DC BIAS EQUATION
• OUTPUT DC BIAS EQUATION
• LINEAR EQUATION WITH SLOPE DETERMINED
BY EXTERNAL RESISTORS
MOSFET BIAS CIRCUIT
VDD
ID
ID
RD
RD
+
VDS
+
-
VGS
VGG
-
RS
+
VDD
VGG
VDS
+
-
VGS
-
RS
INPUT EQUATION
• SETS OR SELECTS DC GATE TO SOURCE
VOLTAGE
• SETS OR SELECTS DC DRAIN CURRENT
• CONSTRUCTED BY PERFORMING KVL ON INPUT
PORTION OF THE CIRCUIT
KVL INPUT EQUATION
 VGG  VGS  I D RS  0
VGS  VGG  I D RS
VGG  VGS
ID 
RS
OUTPUT EQUATION
• SELECTS OR SETS DC DRAIN TO SOURCE
VOLTAGE
• SELECTS OR SETS DC DRAIN CURRENT
• CONSTRUCTED BY PERFORMING KVL ON
OUTPUT PORTION OF THE CIRCUIT
KVL OUTPUT EQUATION
 VDD  I D RD  VDS  I D RS  0
VDS  VDD  I D RD  RS 

1
I D  
 RD  RS

 VDD
VDS  

 RD  RS



LOAD LINE EQUATION
• USED TO SELECT BIAS PARAMETERS VGS, VDS,
AND ID.
 1
I D  
 RD  RS

 VDD
VDS  

 RD  RS



ID
1.5mA
vGS3
1.0mA
Linear, Ohmic,
Triode ROP
Saturation ROP
LOAD LINE
vGS2
0.5mA
vGS1
Cutoff ROP
0mA
0V
2V
4V
6V
vDS
8V
10V
12V
BIASING CIRCUITS
• USED TO ESTABLISH
- VGG (GATE VOLTAGE)
- ID (DRAIN CURRENT)
-VDS (DRAIN TO SOURCE VOLTAGE)
• USES ONE OR TWO POWER SUPPLIES
USING TWO POWER SUPPLIES
VDD
ID
RD
+
VDS
-
RS
VSS
DESIRED BIAS CONDITIONS
VDD  5V
VSS  5V
VGS  2V
VDS  3V
I D  1mA
SELECTION OF RS
 VGS  VSS 
VGS  I D RS  VSS  0  RS 
ID
 2V  5V 
RS 
 RS  3k
1mA
SELECTION OF RD
 VDD  I D RD  VDS  I D RS  VSS  0
I D RD  RS   VDD  VDS  VSS
 VDD  VDS  VSS
RD  
ID


  RS

 5V  3V   5V  
RD  
  3k  RD  4k
1mA


USING ONE POWER SUPPLY
VDD
IX
ID
R1
RD
+
VDS
-
IG = 0
+
VGG
-
+
R2
IX
VGS
-
RS
ID
R1
VDD
RD
+
VDS
-
IG = 0
+
VGG
-
+
R2
VGS
-
RS
DEVELOPMENT OF GATE
VOLTAGE
VDD
IX 
R1  R2
I G  0 
VGG  I X R2
VGG
 R2 
VDD 
 
 R1  R2 
INPUT AND OUTPUT EQUATIONS
VGS  VGG  I D RS
VGG  VGS
RS 
ID
VGG  VGS
ID 
RS
VDS  VDD  I D RD  RS 

1
I D  
 RD  RS

 VDD
VDS  

 RD  RS



DESIRED BIAS CONDITIONS
VGS  1.5V
VDD  5V
VGG  3V
I D  0.5mA
VDS  2V
SELECTION OF R1 AND R2
VGG
 R2 
VGG
R2
VDD  
 

VDD R1  R2
 R1  R2 
3V
R2

5V R1  R2
A  int eger
 R2  A3k, R1  A5  3k
SELECTION OF RS AND RD
VGG  VGS
RS 
ID
3V  1.5V
 RS  3k
 RS 
0.5mA
VDD  VDS
 RS
RD 
ID
RD  3k
5V  2V
 3k
 RD 
0.5mA