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Power Dissipation in CMOS
Two Components contribute to the power
dissipation:
» Static Power Dissipation
– Leakage current
– Sub-threshold current
» Dynamic Power Dissipation
– Short circuit power dissipation
– Charging and discharging power dissipation
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Static Power Dissipation
Leakage Current:
• P-N junction reverse biased current:
io= is(eqV/kT-1)
• Typical value 0.1nA to 0.5nA @room temp.
Vin
• Total Power dissipation:
Psl= i0.VDD
VDD
S
G
MP
B
D
Vo
D
G
B
MN
Sub-threshold Current
• Relatively high in low threshold devices
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S
GND
2
Analysis of CMOS circuit power dissipation

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The power dissipation in a CMOS logic gate can be
expressed as
P = Pstatic + Pdynamic
= (VDD · Ileakage) + (p · f · Edynamic)
Where p is the switching probability or activity factor
at the output node (i.e. the average number of output
switching events per clock cycle).
The dynamic energy consumed per output switching
event is defined as
Edynamic =
i
V dt
DD DD
1 _ switching_ event
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Analysis of CMOS circuit power dissipation
2
2
Edynamic  CLVDD
 2CMVDD
 ESC
2
2
 CloadVDD
 [Cdbp  Cdbn  2(Cgdn  Cgdp )]VDD
 ESC
The first term —— the energy dissipation due to the
Charging/discharging of the effective load capacitance CL.
The second term —— the energy dissipation due to the input-tooutput coupling capacitance. A rising input results in a VDDVDD transition of the voltage across CM and so doubles the
charge of CM.
CL = Cload + Cdbp +Cdbn
CM = Cgdn + Cgdp
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The MOSFET parasitic capacitances
• distributed,

• voltage-dependent, and

• nonlinear.
 So their exact modeling is quite complex.
Even ESC can be modeled, it is also difficult to calculate the
Edynamic.

On the other hand, if the short-circuit current iSC can be Modeled,
the power-supply current iDD may be modeled with the same
method.
So there is a possibility to directly model iDD instead of iSC.
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Schematic of the Inverter
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Analysis of short-circuit current
The short-circuit energy dissipation ESC is due to the railto-rail current when both the PMOS and NMOS devices
are simultaneously on.
ESC = ESC_C + ESC_n
Where
and
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ESC _ c  VDD
E SC _ d  VDD
i
dt
i
dt
n
v0  0 VDD
p
v0 VDD  0
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Charging and discharging currents

Discharging Inverter
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Charging Inverter
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Factors that affect the short-circuit current
For a long-channel device, assuming that the inverter is
symmetrical (n = p =  and VTn = -VTp = VT) and with zero load
capacitance, and input signal has equal rise and fall times (r = f
= ), the average short-circuit current [Veendrick, 1994] is
I mean
1 
3 

(VDD  2VT )
12 VDD
T
From the above equation, some fundamental factors that
affect short-circuit current are:
 W
(

)

t L , VDD, VT,  and T.
ox
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Parameters affecting short cct current
For a short-channel device,  and VT are no longer
constants, but affected by a large number of
parameters (i.e. circuit conditions, hspice
parameters and process parameters).
CL also affects short-circuit current.
Imean is a function of the following parameters (tox is processdependent):
CL, , T (or /T), VDD, Wn,p, Ln,p (or Wn,p/ Ln,p ), tox, …
The above argument is validated by the means of simulation in
the case of discharging inverter,
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The effect of CL on Short CCt Current
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Effect of tr on short cct Current
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Effect of Wp on Short cct Current
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Effect of timestep setting on simulation results
Tr (ps)
0
100
200
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Timestep (ps)
2
4
5
6
8
10
2
4
5
6
8
10
2
5
5
8
8
10
MaxStep (ps)
10
10
10
10
10
20
10
10
10
10
10
20
10
10
20
10
20
20
iMax (uA)
802.6
413.8
336.4
284.9
221
183
73.09
64.4
58.69
65.64
76.13
63.1
50.96
49.78
50.46
50.72
52.08
51.25
iaverage_inT/2 (uA)
1.258
1.264
1.24
1.234
1.245
1.231
1.202
1.213
1.21
1.208
1.207
1.217
1.311
1.295
1.313
1.311
1.311
1.311
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Thank you !
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