Download Lecture 18 - Auburn University

ELEC 5970-001/6970-001(Fall 2005)
Special Topics in Electrical Engineering
Low-Power Design of Electronic Circuits
Power Consumption in a Memory
Vishwani D. Agrawal
James J. Danaher Professor
Department of Electrical and Computer Engineering
Auburn University
http://www.eng.auburn.edu/~vagrawal
[email protected]
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ELEC 5970-001/6970-001 Lecture 18
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Intuitive Architecture
M bits
Word 0
Word 1
Word 2
Storage cell
N words
S0
SN-1
Word N-2
Word N-1
Input-Output (M bits)
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Memory Organization
2L-K
Bit line
Storage cell
AK
AK-1
Word line
AL-1
M.2K
Sense amplifiers/drivers
A0
AK-1
Column decoder
Input-Output (M bits)
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Cell Array Power Management
• Smaller transistors
• Low supply voltage
• Lower voltage swing (0.1V – 0.3V for
SRAM)
– Sense amplifier restores the full voltage swing
for outside use.
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Sense Amplifier
VDD
bit
Sense ampl. enable:
Low when bit lines
are precharged and
equalized
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bit
Full voltage
swing
output
SE
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SRAM Cell
VDD
Precharge
circuit
PC
EQ
WL
BL
BL
Output
bit
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Sense
amplifier
bit
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Hierarchical Organization
Block 0
Block 1
Block P-1
Row
addr.
Column
addr.
Block
addr.
Global data bus
Control
circuitry
Global amplifier/driver
Block selector
I/O
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Power Saving
• Block-oriented memory
– Lengths of local word and bit lines are kept
small.
– Block address is used to activate the
addressed block.
– Unaddressed blocks are put in power-saving
mode; sense amplifier and row/column
decoders are disabled. Power is maintained
for data retention.
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1.3μ
8-kbit SRAM
1.1μ
900n
0.13μ CMOS
700n
500n
300n
0.18μ CMOS
100n
0.0
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7x increase
Leakage current (Amperes)
Static Power
0.6
1.2
1.8
Supply voltage
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Adding Resistance in Leakage Path
VDD
Low-threshold transistor
sleep
VDD.int
SRAM
cell array
SRAM
cell array
SRAM
cell array
VSS.int
sleep
GND
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Lowering Supply Voltage
VDD
Sleep = 1, data
retention mode
VDDL= 100mV for 0.13μ CMOS
sleep
SRAM
cell array
SRAM
cell array
SRAM
cell array
GND
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References
• K. Itoh, VLSI Memory Chip Design,
Springer-Verlag, 2001.
• J. M. Rabaey, A. Chandrakasan and B.
Nikolić, Digital Integrated Circuits, Upper
Saddle River, New Jersey: Pearson
Education, Inc., 2003.
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