Download A New Successive Approximation Architecture for Low

A New Successive Approximation
Architecture for Low-Power Low-Cost A/D
Converter
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL.38, NO.1, JANUARY 2003
Chi-sheng Lin and Bin-Da Liu, Senior Member, IEEE
指導教授：汪輝明
學
生：陳柏宏
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Outline
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Abstract
Introduction
Basic architecture of successive approximation ADC
The ISA (improved successive approximation) -ADC circuit
design
System design of the parallel - like ISA - ADC
Low – voltage circuit design of the ISA – ADC
Experimental result
Conclusion
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Abstract
 A new 6-bit 250MS/s analog-to-digital converter is proposed
for low-power low-cost CMOS integrated system.
 The experimental results indicate that this ADC works up to
250MS/s with power consumption less then 30mW at 3.3V.
 The ADC occupies only 0.1mm2 with the TSMC 0.35-μm
single poly quadruple metal (SPQM) CMOS technology.
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Introduction
 In this paper, a novel circuit for low-power low-cost 6-bit
CMOS ADC is presented.
 Based on the ISA-ADC architecture, a parallel-like ISA-ADC
architecture for high-speed low-resolution applications is
developed.
 The proposed converter has a simple hardware design and
low-accuracy comparator and therefore, is suitable for lowpower low cost standard CMOS technology VLSI
implementation.
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Basic architectures of successive approximation
ADC
 The architecture of a general SA-ADC usually consists of a
rail-to-rail analog comparator, a digital-to-analog converter
and a successive approximation register (SAR) as show in
Fig. 1.
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Basic architectures of successive approximation
ADC
 The input signals of this comparator is expressed by
Vin  V fb
 To solve this problem, another SA-ADC architecture was
developed to simplify the comparator require, as shown in
Fig. 2
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Basic architectures of successive approximation
ADC
 The input signals of this comparator is expressed by
Vin  V fb  0
 Where D is the output digital code for the ADC and
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The ISA-ADC circuit design
 Fig. 3 shows the circuit diagram of the ISA-ADC
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The ISA-ADC circuit design
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(3)
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The ISA-ADC circuit design
Vin  DVref  0
Vin  (1  D )Vref  Vref
Vin
 2n
D0  
 Dn 1
  n 
 ... 
Vref  Vref
n 
2 
 2
2
Vin
 23
D0  
D
 D2
  3 
 21 
Vref  Vref
3 
2
2 
 2
2
Vin 
Vin
Vin
Vin
Vin
Vin
23   2 2 D2  21 D1  2 0 D0 
Vref  Vref
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2 2 1  D2   21 1  D1   2 0 1  D0   2 0

Vref  Vref
3
2
2 2 D2  21 D1  20 D0
1

V

V

Vref
ref
ref
3
3
2
2
1
 DVref  Vref  3 Vref
2
23  1
 DVref 
Vref
23
 DVref
23  1

Vref
4
2
2
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The ISA-ADC circuit design
 Fig. 4 shows the circuit diagram for the low-cost, low power,
high-speed comparator.
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The ISA-ADC circuit design
 To force Vout to Vdd /2, a suitable correction voltage must be
applied between the input pins.
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The ISA-ADC circuit design
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Using (3), the input signals of the comparator is rewritten
as

Since the practical comparator has an input offset voltage
when using Fig. 5(a), the output signal of the comparator
is, therefore, expressed by
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The ISA-ADC circuit design
 Fig. 5(b) shows the offset compensated circuit of the low
accuracy comparator.
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The ISA-ADC circuit design


 The mixed-mode subtracter (MMS) function Vin  DVref  / 2
remains a challenge. To explain how this function works, it is
rewritten as
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The ISA-ADC circuit design
 Using (6), the MMS circuit is implemented using the R-2R
ladder architecture. Fig. 6 shows a MMS circuit diagram with
a 4-bit size.
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System design of the Parallel-Like ISAADC
 Fig. 7 gives the parallel-like architecture design based on the
ISA-ADC circuit with a 4-bit size.
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System design of the Parallel-Like ISAADC
 Using (4), the CMP3 component operation is written as
 The CMP2 component operation is written as
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System design of the Parallel-Like ISAADC
 The CMP1 component operation is written as
Vin D3
D2
2 1
 Vref  Vref 
 n 1 Vref  Vos1
2
4
8
16
2
Vref
n
 The CMP0 component operation is written as
Vin D3
D2
D1
1
2n  1
 Vref  Vref  Vref  Vref  n 1 Vref  Vos 0
2
4
8
16
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2
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System design of the Parallel-Like ISAADC
 Fig. 8 shows the simulation results for the proposed parallellike ISA-ADC with the worst input pattern.
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Low-voltage circuit design of the ISA-ADC
 Using (3), it appears that the comparator in the proposed
circuit only compares with half of the Vref voltage level
 Using (4), this expression is rewritten as
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Low-voltage circuit design of the ISA-ADC
 For the MMS function, using (10), it is rewritten as
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Low-voltage circuit design of the ISA-ADC
 Fig. 9 shows the modified MMS circuit diagram with a 4-bit
size for low-voltage ISA-ADC.
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Low-voltage circuit design of the ISA-ADC
 The simulation results for the parallel-like ISA-ADC with 6bit size under 0.8-V supply voltage are shown in Fig. 10.
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Experimental result
 The maximum conversion rate of the chip is 128 x 1.95MHz
= 250MS/s with power consumption less then 30 mW under
3.3-V supply voltage.
 The measured results showed that the maximum converter
rate of the converter is 1 MS/s under 0.8-V supply voltage.
 With a 1.95 MHz triangle-wave input, the INL is less then
±0.65 LSB and the DNL is less then ±1 LSB, respectively.
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Experimental result
 The DNL and INL measured results for the chip working
under 3.3-V supply voltage are display in Fig. 11.
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Experimental result
 The area of the core is 480μm x 220μm using the TSMC
0.35μm SPQM CMOS process technology.
 At 250MS/s with a 1MHZ full-scale (Vdd = 3.3V) tone input,
the measured signal-to-(noise + distortion) ratio (SNDR) is
33.6dB.
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Experimental result
 Fig. 14 shows the measured results of ENOB with varying
input frequencies.
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Experimental result
 The performance is summarized in Table I.
 A comparison of the proposed ISA-ADC with the previously
report 6-bit ADCs is given in Table II.
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Conclusion
 The experimental results showed that the proposed circuit
achieves 250 MS/s with power consumption less then 30
mW at 3.3 V.
 Based on a novel mixed-mode subtracter, the overall power
consumption and system complexity are reduced as well.
 This device is suitable for standard CMOS technology VLSI
implementation, and it is well applied when embedded into
system-on-chip (SoC) circuit designs.
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