Download 32 BIT PARALLEL LOAD REGISTER WITH CLOCK GATING

PRARDIVA MANGILIPALLY
ELEC 6270
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Objective
Basic idea
Basic gating circuit
Modified clock gating circuit
Design platform
Results
Conclusion
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To measure the average power for a 32 bit
parallel load register with and without clock
gating.
To compare the results for the same.
To study the effect of clock gating on power
consumption for a 32 bit parallel load
register.
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Clock gating is one of the power saving techniques
in which additional logic is added to a circuit to
prune the clock tree ,thus disabling portions of
circuitry so that flipflops do not change state.As a
result switching power goes to zero.
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Latchfree clock gating circuit
Tools used: Modelsim, leonardo, Design
Architect, Eldo
Technology: tsmc018
Clock frequency: 50MHz
Operating voltage: 1.8V
Without clock gating
Average power: = 242.6818U W
With clock gating
Average power: 42.8374U W
Without clock gating
Average power: 244.0567UW
With clock gating
Average power: 27.4138UW
Without clockgating
Average power:457.2622uW
With clock gating
Average power: 628.8430U W
WITHOUT CLOCKGATING:
AVERAGE POWER:357.8213UW
WITH CLOCK GATING
AVERAGE POWER:337.1065UW
WITHOUT CLOCKGATING
AVERAGE POWER:355.11064UW
WITH CLOCKGATING
AVERAGE POWER:331.2031UW
WITHOUT CLOCKGATING:
AVERAGE POWER:352.7703UW
WITH CLOCKGATING:
AVERAGE POWER:324.1347UW
WITHOUT CLOCKGATING
AVERAGE POWER:344.7696UW
WITH CLOCKGATING
AVERAGE POWER:337.4078UW
WITHOUT CLOCK GATING:
AVERAGE POWER:288.4402UW
WITH CLOCK GATING:
AVERAGE POWER:165.1852UW
WITHOUT CLOCKGATING:
AVERAGE POWER:289.1212UW
WITH CLOCKGATING:
AVERAGE POWER:146.8568UW
Without clock
gating
With clock
gating
TRANSITION
DENSITY
EXPECTED POWER
(UW)
OBSERVED
POWER
(UW)
EXPECTED
POWER
(UW)
OBSERVED
POWER
(UW)
POWER
REDUCTION
(%)
0.0000
244.0512
244.0567
68.7008
27.4138
88.77
0.0004
242.6944
242.6818
70.1134
42.8374
82.35
0.1000
262.4961
289.1212
182.0272
146.8568
49.21
0.1024
289.1168
288.4402
170.3126
165.1852
42.73
0.2500
357.7568
357.8213
340.1931
337.1065
5.51
0.5000
457.1456
457.2622
655.6832
628.840
-37.5
Average Power Comparisons
Average Power(uW)
700
600
500
400
without
clockgating
300
with clockgating
200
100
0
best
case
worst Typical
case
case
Power Savings in %
Power Savings Chart
100
80
60
40
20
0
-20
-40
-60
88.77
82.35
49.21
42.73
0
0.0004
0.1
0.1024
1
2
3
4
0.25
5.51
5
0.5
6
-37.5
Transition Density
transition density
power saving
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Clock gating technique effectively reduces dynamic power in
most of the cases.
However,it increases power when there are transitions in
every clock cycle.This increase is due to the extra power
consumed by the ex-nor and nor gates in the clock gating
circuit which account to about 58% increase in total hardware.
If this increase in hardware could be reduced then the power
savings can be increased even in the worst case which calls
for the implementation of a different clock gating circuit or
the usage of low power ex-or’s discussed in the class.
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Class lecture slides at
http://www.eng.auburn.edu/~vagrawal/ COURSE/
E6270_Spr09/course.html
Frank Emnett and Mark Biegel, Power Reduction
Through RTL Clock Gating, SNUG2000(This paper
discusses a method to avoid premature truncation
of the clock).
THANK YOU