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Particle pixel detectors in high-voltage CMOS
technology
Ivan Peric
University of Heidelberg
IWLC 2010 – Ivan Peric
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Pixel detector in HV CMOS technology
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Monolithic pixel sensor
100% fill-factor
In-pixel CMOS signal processing
Excellent SNR (seed 21 μm-pixel SNR for high energy betas > 80)
Allows thinning below 50 μm without signal decrease
Good timing properties (theoretically 40 ps signal collection time)
Radiation hard (tested to 50 MRad (x-rays) and 1015 neq (protons))
Not expensive (standard technology used, wafer run costs 98 k€)
IWLC 2010 – Ivan Peric
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The detecor stucture
Based on twin-well structure
P-substrate
Deep n-well
Pixel electronics in the deep n-well
NMOS transistor
in its p-well
PMOS transistor
The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed
directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as
well.
IWLC 2010 – Ivan Peric
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“Smart” diode array
Based on twin-well structure
P-substrate
Deep n-well
Pixel electronics in the deep n-well
NMOS transistor
in its p-well
PMOS transistor
Smart diode
IWLC 2010 – Ivan Peric
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“Smart” diode array in HV CMOS technology
High voltage deep n-well used
P-substrate
Deep n-well
Pixel electronics in the deep n-well
NMOS transistor
in its p-well
PMOS transistor
E-field
Particle
14 μm at 100V bias
(MIP: 1080e from depleted layer)
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
IWLC 2010 – Ivan Peric
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Signal detection
3.3 V
CR-RC
Comparator
CSA
AC coupling
-50 V
N-well
P-substrate
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Strong points
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1) CMOS in-pixel electronics
2) Good SNR
3) Fast signal collection
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4) Thinning possible
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Standard technology without any adjustment is used
Many industry relevant applications of HV CMOS technologies assure their long tern
availability
6) High tolerance to non-ionizing radiation damage
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Since the charge collection is limited to the chip surface, the sensors can be thinned
5) Price and technology availability
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Theoretically 40ps
High drift speed
Short drift path
7) High tolerance to ionizing radiation
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Deep submicron technology
Radiation tolerant design can be used
Radiation tolerant PMOS transistors can be used (in contrast to MAPS with high-resistance
substrate)
IWLC 2010 – Ivan Peric
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Drawbacks
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1) Capacitive feedback
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must be taken into account when the pixels are designed and simulated.
In some cases the capacitive feedback can be of use, for instance if provides a feedback
capacitance for the charge sensitive amplifier.
Despite some limitations, we can implement the majority of important pixel circuits in
CMOS, like the charge sensitive amplifier, shaper, tune DAC, SRAM…
CMOS logic gates in pixels should be avoided – current mode logic can be used
instead
2) Relatively large size of the collecting electrode
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However the high voltage deep n-well has relatively small area capacitance.
Typical values for the total n-well capacitance are from 10fF (small pixels and simple pixel
electronics) to 100fF larger CMOS pixels.
Despite of the capacitance, we achieve excellent SNR values.
IWLC 2010 – Ivan Peric
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Pixel i
Pixel i+1
P-Well
HV deep N-well
14 m @ 100V (1080 e)
Depleted
P-substrate
IWLC 2010 – Ivan Peric
Not depleted
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Project overview
Testbeam DESY
DUT
EUDET telescope
First chip – CMOS pixels
a) supply
b) Power
Hit detection in pixels
220 Trigger ID
Sr-90, Regular pixel, 55V
and cont. signals
Binary
RO
CR-RC
200 Comparator
for the readout chip
Pixel size 55x55μm180
Noise:Testbeam
60e
DUT
160CERN
MIP seed
pixel
signal
1800
e
1.5 mm
140
ADC channel
Time resolution
200ns
CSA
120
60V bias voltage
(3 batteries)
efficiency
Power supply
Testchip
MIP
Signal:
1
100
Efficiency
and cont. signals
2000e/1.17
=
1710 e
60
80
for the sensor
100%
Frame readoutLow
- monolithic
Bumpless
hybrid detector
0.9
energy peak:
60 SpS - 120GeV protons)
Pixel matrix
MIP spectrum (CERN
90%
40
CCPD1 Chip
PM1 1.080
Chip e
0.8
800
50
80%
Bumpless hybrid detector
20
AC coupling
-50 V
Pixel size 21x21μm
seed
pixel
0.7
70%
Based on capacitive chip to chip
0
700
Frame mode readout
0
100
200
300
400
500
600
700
800
3MSP
signal
transfer
40
60%
4 PMOS
pixel electronics
PCB
0.6
600
Pixel size 78x60μm
wholeToT/Clk
cluster
128 on chip ADCs
50%
1,1
RO type: capacitive
Noise: 90e
0.5
Regular pixel, 55V
40%
500
30
1,0
Noise: 80e Purity
Test-beam: MIP signal 2200e/1300e
Efficiency
30%
Readout chip (CAPPIX)0,9
MIP signal 1800e
EfficiencyFe-55
> 85% (timing problem)0.4
400
0,8
20%
Spatial
resolution 7μm
Sr-90
20
0.3
0,7
Uniform
detection
10%
300 and signals
Pads for power
0,6
N-well
0.2
CCPD2
Chip
Readout
electrodes
3.5
4.5
5.5
6.5
7.5
8.5
9.5 20010.5 11.5
T 2.5
10
0,5
USB
Edgeless CCPD
^
0.1
0,4
4.5
5.0
6.0
6.5
7.0
7.5
8.0
8.5
connector
T 4.0
Pixel 5.5
size 50x50μm
100and analog supply
PCB with PPGA
0,3
and cluster cut [SNR]
0
Noise:Seed
30-40e
0
voltage regulators/DACs
0
40
60
80
100
120
0,220
Time resolution 300ns
0
Chip
pixelPM2
x
0
5
10
15
20
25
30
35
40
45coordinate
50
0,1
SNR 45-60
P-substrate
Noise: 25e, Seed MIP
SNR ~ 100
SNRplanned
0,0
Irradiations of test pixels
0
100
200
300 Test
400 beam
500
600
700
800
60MRad – SNR 22 at 10C (CCPD1)
ToT/Clk
15n
10Sensor
at 10C (CCPD2)
chip50(CAPSENSE)
eq SNR
pixels
IWLC 2010Sensor
– Ivan Peric
Number of hits
2.7 mm
~hit probability
pixel coordinate y
count
3.3 V
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Experimental results
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Measurements with HVPixelM2
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HVPixelM2 chip
ADC channel
Pixel matrix
2.7 mm
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HVPixelM2 chip
10000001000
Pixel matrix
Row-control („Switcher“)
 Pixel size: 21 X 21 m
 Matrix size: 2.69 X 2.69 mm (128 X
128)
 Possible readout time/matrix: ~
simulated 40 s (tested 160 s/matrix)
 ADC: 8 – Bit
 Measured power:
 3 μW/pixel analog
 8 μW/pixel digital at 160 s/matrix (can
be reduced to 2.3 μW/pixel for 40 s/matrix by
lowering the digital voltage and resizing the
flip flops)
Amplifier
Ramp gen.
Comparator
8 LVDS
Digital output
Counter
IWLC 2010 – Ivan Peric
ADC
Latch
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Noise measurement and 55Fe spectrum (HVPixelM2)
55
Fe, 1 pixel, 76 ADU, (1660e)
Noise 1.1 ADU (24e)
1.0
Noise: 24e
DKS used
55Fe
1660e
~ number of signals
0.8
0.6
0.4
0.2
0.0
50
60
70
80
90 100 110 120 130 140 150 160 170
ADU
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High-energy beta spectra (HVPixelM2)
60Co
55Na
betas (about 10% higher signals than MIPs)
Seed signal: 1700e
Cluster signal: 2250e
Noise: 21e
Seed SNR: 81
Cluster signal/seed noise: 107
1.0
betas
Seed signal: 1900e
Cluster signal: 3300e
Noise: 21e
Seed SNR: 90
Cluster signal/seed noise: 157
Noise, 1 pixel (21e)
Na, 1 pixels (1900e)
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Na, 2 pixels (2200e)
22
Na, 3 pixels (2500e)
22
Na, 9 pixels (3300e)
1.0
Noise, 1 pixel (21e)
Co, 1 pixel (1700e)
60
Co, 2 pixels (1800e)
60
Co, 3 pixels (1900e)
60
Co, 4 pixels (2250e)
22
60
0.8
~number of signals
~number of signals
0.8
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0
1000
2000
3000
4000
5000
6000
signal amplitude [e]
7000
8000
0
1000
2000
3000
4000
5000
6000
7000
8000
signal amplitude [e]
Estimated MIP seep pixel SNR 70
IWLC 2010 – Ivan Peric
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High-energy beta spectra (HVPixelM2)
1.0
Noise, 1 pixel (23e)
22
Na, 6 pixels (3300e)
number of signals
0.8
0.6
0.4
0.2
0.0
0
2000
4000
6000
8000
10000
12000
signal amplitude [e]
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Radiation tolerance
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We expect a good tolerance to non-ionizing damage thanks to the small drift distance
and high drift speed in the depleted area. Due to high dopant density the type
inversion should occur at higher fluencies.
Concerning the ionizing damage, we can benefit from the properties of the used deep
submicron CMOS technology. In contrast to the most of the MAPS, we can rely on
PMOS transistors inside pixels that are more radiation tolerant than NMOST.
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Irradiation with protons (1015 neq/cm2, 300 MRad)
55Fe
55Fe
spectrum and RMS noise
Not irradiated
Room temperature
1.0
RMS Noise 12 e
RMS Noise 0.5mv (12e)
Fe 70mV (1660e)
Room temperature
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spectrum, RMS noise
Irradiated
10C
RMS Noise 77 e
1.0
0.8
~number of signals
0.8
~ number of signals
RMS Noise, 2.8mv (77e)
Fe, 60mV (1660e)
Temperature 10C
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Irradiated with protons to 10 neq
55
0.6
0.4
0.2
0.6
0.4
0.2
0.0
0.0
0.00
0.02
0.04
0.06
signal amplitude [V]
IWLC 2010 – Ivan Peric
0.08
0.10
0.00
0.02
0.04
0.06
0.08
0.10
signal amplitude [V]
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Irradiation with protons (1015 neq/cm2, 300 MRad)
RMS Noise (40e)
Fe x-ray spectrum (Peak: 1660e)
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Na beta spectrum (Maximum: 3750e)
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~number of signals
1.0
0.8
SNR = 93
0.6
0.4
0.2
0.0
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
signal amplitude [V]
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Summary
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We have developed a new pixel sensor structure (smart diode array) for
high energy physics that can be implemented in a high voltage CMOS
technology.
The sensor has 100% fill-factor and can have in-pixel electronics
implemented with p- and n-channel transistors.
We have implemented the sensor structure in various variants:
1) Sensor with in-pixel hit detection and sparse readout,
2) Sensor with fast rolling-shutter readout and simple pixel electronics,
3) Hybrid sensor based on capacitive chip to chip signal transfer.
We measure excellent SNR in all three cases.
We have done a test-beam measurement with the first version of the frame
readout detector with good results.
The SNR of the second chip version is four times better.
Excellent seed pixel SNR of almost 100 has been achieved.
We have irradiated the chips with neutrons, protons and x-rays to test
radiation tolerance.
After irradiation with protons up to very high fluence 1015 neq/cm2 and dose
300MRad, we have still very large SNR (>40) for high energy beta particles
at nearly room temperatures (10C).
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Outlook
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The engineering run in the used technology costs only 98k €
By proper arrangement of the dices, we can obtain long monolithic multireticle sensors with 12cm length and 1cm width
We would have 8 such modules per wafer and one engineering run could
give us up to 48 modules
We are confident that the sensor technology has achieved such a degree of
maturity so that it can be considered as a good candidate for future particle
physics experiments
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Multi-reticle module
Module
Chip2
Chip2
Pads
Chip1
Reticle1
Chip to chip connections
Chip to reticle edge distance = 80 um
Chip1
Reticle2
2.0 cm
Very long low-cost pixel modules with (almost) no insensitive area can be produced
Reticle-reticle connections can be made easily by wire bonding
Instead of wire-bonding, an extra metal layer can be used as well
IWLC 2010 – Ivan Peric
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Multi-reticle module
Module (length. 12 cm, width 1cm, the figure is not scaled)
chip to chip connections
Pads for power and IO signals
Chip (reticle 2)
Chip (reticle 3)
Carrier
Large sensitive area without material
Interaction region
Very low-mass only silicon modules are possible as well (similar to DEPFET module for Belle II)
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SDA long module
1 cm
12 cm (one half of the module shown)
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Sensor types
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Frame RO type 1: (for ILC)
(Scaling of the existing PM design)
Half module size 1x6cm
Pixel size 40x40μm
Pixels 250x1500
RO time 80μs/matrix
Resolution 8bit/pixel
Power 900mW/module (150mW/cm2)
Data output width 96 bits @ 400Mbit
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Frame RO type 2 (in-pixel DKS and binary readout): (for Belle II, ILC...)
(new Design)
Half module size 1x6cm
Pixel size 40x40μm
Pixels 250x1500
RO time 10μs/matrix
Resolution 1bit/pixel
Power 900mW/module (150mW/cm2)
Data output width 96 bits @ 400Mbit
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Continuous RO type (in-pixel hit-detection): (for LHC, Belle II...)
(Scaling of the existing design plus new readout periphery block)
Half module size 1x6cm
Pixel size 40x80μm
Pixels 250x750
Time resolution: 50-100ns
Power 1000mW/module (167mW/cm2)
IWLC 2010 – Ivan Peric
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Sparse RO typ
2cm - chip
chip2
chip1
chip3
RO
1.2cm
Pixel matrix (250x250)
64
Pixel matrix (250x250)
Wire bond
RO
DO
IWLC 2010 – Ivan Peric
6cm - module DO
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Sparse RO typ
125 wires
FB
L
A
C
DAC
Deep N-Well
Pixel 1
Deep N-Well
Deep N-Well
Pixel 2
Pixel 3
125 wires
FB
350nm: 80μm – 125 lines
L
180nm: 40μm – 125 lines
A
C
DAC
Deep N-Well
IWLC 2010 – Ivan Peric
Deep N-Well
Deep N-Well
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Sparse RO typ
Pixels
Hit processing units
Pix
col adr,TS
LdHit
Res NextHit
PriHit
HitOut
Ck
Wr,RdLIFO
HitOutSync
Ck
LdData
Buffers - LIFO
NextData
PriData
DataOutSync
IWLC 2010 – Ivan Peric
DataOut
col/row adr,TS
Data processing units
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Time walk for 5μW pixel amplifier
Output of the Pixel amplifier
M0(89.99ns)
M0(89.99ns)
M0(89.99ns)
600e
1200e
Y0 (mV)
1800e
IWLC 2010 – Ivan Peric
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Time walk for 5μW pixel amplifier
Y0 (mV)
Output of the Pixel amplifier
M0(89.99ns)
M0(89.99ns)
M0(89.99ns)
M0(89.99ns)
M1(137.4ns, -41.82mV)
50ns time walk
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•
Thank you!
IWLC 2010 – Ivan Peric
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