Download FUTURE DIRECTIONS IN BEHAVIORAL MODELING

Top-Down Design
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Design Starts
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IBS 2001
Mixed-Signal
Digital
• MS design starts reaches 70% of total by 2006
• MS design starts increasing at 9% CAGR
– Pure digital falling at 12.5% / year
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Design Challenge: Size and Complexity
• Increasing complexity as circuits become larger
– Increasing integration
– To reduce cost, size, weight, and power dissipation
– Digitalization
– Both digital information and digital implementation
• Increasing complexity of signal processing
– Implementation of algorithms in silicon
– Adaptive circuits, error correction, PLL’s, etc.
• Designers must improve their productivity to keep up
Slides from EPD 2001, AACD 2000
Productivity:
Improving CAD is not Enough
“Fundamental improvements in design methodology
and CAD tools will be required to manage the
overwhelming design and verification complexity”
Dr. H. Samueli, co-chairman and CTO, Broadcom Corp. Invited Keynote
Address, "Broadband communication ICs: enabling high-bandwidth
connectivity in the home and office", Slide supplement 1999 to the Digest of
Technical Papers, pp. 29-35, International Solid State Circuits Conference, Feb
15-17, 1999, San Francisco, CA
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Design Productivity
• Huge productivity ratio between design groups
– As much as 14x (Collett International, 1998)
• In a fast moving market
– Cannot overcome this disparity in productivity by working harder
– Must change the way design is done
• Cause of poor productivity: Using a bottom-up design style
– Problems are found late in design cycle, causing substantial redesign
– Simulation is expensive, and so usually inadequate
– Inadequate verification requires silicon prototypes
– Today’s designs are too complex for bottom-up design style
– Too many serial dependencies
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What is Needed
• To handle larger and more complex circuits
– Need better productivity
– Need divide and conquer strategy
• To address time-to-market
– Must effectively utilize more designers
– Must reorganize design process
– More independent tasks
– Reduce number of serial steps
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The Solution
• A formal top-down design process …
– That methodically proceeds from architecture to transistor level
– Where each level is fully designed before proceeding to next level
– Where each level is fully leveraged in design of next level
– Where each move is verified before proceeding
• Careful verification planning involving ...
– System verification through simulation
– Mixed-level verification through simulation
– A modeling plan that maximizes efficacy and speed of simulation
– Full chip simulation only when no alternatives exist
• Test development that proceeds in parallel with design
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Architectural Exploration & Verification
• Rapidly explore and verify architecture via simulation
– Using Verilog-AMS provides a smooth transition to circuit level
– VHDL-AMS or Simulink could also be used, but more cumbersome
• Provides greater understanding of system early in design
process
– Rapid optimization of architecture
– Discard unworkable architectures early
• Moves simulation to front of design process
– Simulation is much faster
– Block specs driven by system simulation
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Partitioning
• Find appropriate interfaces and partition
– Clever partitioning can be source of innovation
– Joining normally distinct blocks can payoff in better performance
– LO and mixer, S&H and ADC, etc.
– Budget specifications for blocks
– System simulation and experience used to set block specifications
– Document interfaces
• Formal partitioning supports concurrent design
– Better communication
– Design of blocks proceeds in parallel
– Allows more engineers to work on the same project
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Pin-Accurate Top-Level Schematic
• Develop pin-accurate top-level schematic
– Behavioral models represent the blocks
– Faithfully represents block interfaces
– Levels, polarities, offsets, drive strengths, loading, timing, etc.
• Distribute to every member of the team
– Acts as executable specification and test bench
– Acts as DUT for test program development
• Owned by chip architect
– Cannot be changed without agreement from affected team members
– Changes to interfaces not official until TLS updated and redistributed
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Mixed-Level Simulation (MLS)
• Verify circuit blocks in context of system
– Individual blocks simulated at transistor level
– Rest of system at behavioral level
• Simulate with pin-accurate block models
– Verifies block interface specifications
– Eases integration of completed blocks
• Only viable approach to verify complex systems
– Can improve simulation speed by order of magnitude over full
transistor level simulation
Simulation and Modeling Plans
• Identify areas of concern, develop verification plans
– Maximize use and efficacy of system-and mixed-level simulation
– Minimize need for full-chip transistor-level simulation
• Modeling plan developed from simulation plan
– There may be several models for each block
– Several simple models often better than one complex one
– Consider loading, bias levels and headroom, etc.
• Developed and enforced by the chip architect
• Up front planning results in ...
– More complete and efficient verification
– Fewer design iterations
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SPICE Simulation
• Use selectively as needed
– Mixed-level simulation
– Verify blocks in context of system
– Hot spots
– Critical paths
– Start-up behavior
• The idea is not to eliminate SPICE simulation, but to ...
– Reduce the time spent in SPICE simulation while ...
– Increasing the effectiveness of simulation in general
Top-Down Design Is ...
• A way of trading ...
– An up-front investment in planning and modeling
• For ...
– A well controlled design process
– More predictable
– Fewer unpleasant surprises
– Fewer design iterations
– More parallelism
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Case Study:
Disk Read Channel (circa `96)
• Impossible to simulate at circuit level
– >10,000 transistors
– 2000 cycles needed to train adaptive circuits
– Predicted simulation time > 1 month
• Impossible to simulate blocks individually
– System involved complex feedback loop
– Unable to predict closed-loop performance from measurements on
individual blocks
– Difficult to verify blocks outside feedback loop
• Mixed-level simulation was only feasible approach
– 2000 cycles with one block at circuit level overnight
Success Story:
Cadence MS Design Services (circa `98)
• Over 40 ICs designs in the past two years
– All 40 ICs were functional on the first pass
– 28 met full specification
– 10 required a metal mask change to meet specs
– Only two ICs needed changes in silicon to meet specs
• Average is 3 months for complex mixed-signal designs
– Wireless
– Smart Power
– A/D and D/A
– High Voltage Interface Drivers
– Multimedia/Imaging – Network Transceivers/Phy
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Verilog-AMS
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Verilog-AMS
• Superset of Verilog and Verilog-A
– Support both discrete-event and
continuous-time modeling
• Supports mixed-level simulation
– A critical part of a formal top-down
design flow
– Supports both system- and circuitlevel modeling
Digital
Analog
System
System
Gate
Circuit
Verilog
Verilog-A
Verilog-AMS
Verilog-AMS
• Combines Verilog, ...
– Discrete-event / discrete-value simulation
• Verilog-A, …
– Continuous-time / continuous-value simulation
– Signal flow modeling
– Conservative modeling
• And some extras
– Discrete-event / continuous value simulation
– Automatic interface element insertion
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Verilog Example: D Flip-Flop
Symbol
DFF1
Data
Q
Clock
Qb
Reset
Description
Initially set Q to Qinit.
At each positive edge of Clock,
If Reset is not high then set Q to Data.
At each positive edge of Reset, set Q low.
Always set Qb to be the inverse of Q.
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Actual Code
module DFF1 (Q,Qb,Data,Clock,Reset);
output Q,Qb; input Data,Clock,Reset;
parameter Qinit = 0;
reg Q;
initial Q=Qinit;
always @(posedge(Clock))
if (!Reset) Q=Data;
always @(posedge(Reset)) Q=1’b0;
assign Qb = ~Q;
endmodule
D Flip-Flop Code, Annotated
module DFF1 (Q,Qb,Data,Clock,Reset);
output Q,Qb; input Data,Clock,Reset;
parameter Qinit = 0;
reg Q;
Signals assume single-bit digital default
initial Q=Qinit;
Initial section evaluates just once
always @(posedge(Clock))
if (!Reset) Q=Data;
Always is a loop that runs constantly:
Wait for positive clock edge. Then,
If the Reset signal isn’t high,
Set register Q to equal the Data input.
always @(posedge(Reset)) Q=1’b0;
Wait for positive edge of Reset, then
Set Q to equal (1-bit binary) zero.
assign Qb = ~Q;
endmodule
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A ‘reg’ is a 1-bit variable
Define Qb output to be logical
inversion of the Q output. Qb updates
whenever Q changes.
Behavioral Constructs in Verilog
• Process – an independent behavioral agent
– initial blocks – runs once then terminates
– always blocks – runs repeatedly forever
– assign statements – continuously applied
• Register – holds values passed between processes
• Events – changes in the value of a register
– @ statements make processes sensitive to events
– Processes create events when they assign values to registers
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Constructs Needed for Analog Modeling
• To model analog circuits one needs
– A new type of interconnection point (a node)
– Multiple floating contributors
– Value resolved by simultaneous application of Kirchhoff’s laws
– Potentials around a loop must sum to zero
– Flows into a node must sum to zero
– Value varies continuously versus time
– Supports both electrical and non-electrical signals
– A new type of process (analog)
– A block that is continuously applied (like assign statement)
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Verilog-A
• Syntax based on Verilog-HDL
• Able to model analog circuits and systems
– Signal-flow models
– Model relates potentials only
– Useful for abstract models
– Top-level models in top-down design
– Conservative models
– Model relates potentials and flows
– Device modeling and loading at interfaces
– Both are compatible in Verilog-A
– Freely interconnect
– Written in same style
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Potentials and Flows
Potential
Resistor
a
–
Flow
+
V(a,b)
I(a,b)
b
module resistor (a, b);
electrical a, b;
parameter r = 1;
analog
V(a,b) <+ r*I(a,b);
endmodule
Conservative
Model
(potential & flow)
+
V(in)
–
+
V(out)
–
Potential
Potential
Amplifier
module amp (out, in);
output out; input in;
voltage out, in;
parameter a = 1;
analog
V(out) <+ a*V(in);
endmodule
Signal-Flow
Model
(potential only)
Signal-Flow Modeling
• Verilog-A supports extended signal-flow modeling
– Signal may be potentials (voltages) or flows (currents)
– Signals may be floating / differential
– Signal-flow and conservative models may be freely interconnected
Voltage Diff Amp
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Current Diff Amp
module amp (po, no, pi, ni);
output po, no; input pi, ni;
voltage po, no, pi, ni;
parameter a = 1;
module amp (po, no, pi, ni);
output po, no; input pi, ni;
current po, no, pi, ni;
parameter a = 1;
analog
V(po,no) <+ a*V(pi,ni);
endmodule
analog
I(po,no) <+ a*I(pi,ni);
endmodule
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Conservative Models
• Nodes: points where branches interconnect
• Branches: Paths of flow between nodes
• Branch equations: relate flow and potential of each branch
• Kirchhoff’s laws: relate flows and potentials at each node
• User gives branch equations in the form of behavioral models
• User connects branches to nodes using structural models
• Simulator finds potentials and flows that satisfies branch
equations and Kirchhoff’s laws.
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Nodes and Branches
• Node: a interconnection point
– Assumed to be infinitesimally small
– No accumulation of flow on node
– No potential difference across node
• Branch: a path between two nodes
– No accumulation of flow on branch
– What goes in must come out
– Branch potential is potential difference between nodes
–
+
Node
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Branch
Node
Modules and Ports
• Module: a collection of nodes and branches
– Possibly in the form of submodules
• Port: interface that allows branches in module to connect to
nodes outside module
Submodule
Port
Node
Branch
Module
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Disciplines
• Declares the types of nodes, ports, and branches
– Specify natures for potential and/or flow
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Conservative
discipline electrical
potential Voltage;
flow Current;
enddiscipline
Signal-Flow (Potential)
discipline voltage
potential Voltage;
Empty
discipline empty
Signal-Flow (Flow)
discipline current
enddiscipline
flow Current;
enddiscipline
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enddiscipline
Nature
Natures
• Signal type declarations
– Use in discipline declarations or other nature declarations
– Specifies a set of attributes associated with a signal type
– Required attributes
– absolute tolerance (real number)
– units (string)
– access function (name)
– Optional user- and simulator-defined attributes
Voltage
nature Voltage
abstol = 1u;
units = “V”;
access = V;
endnature
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Current
nature Current
abstol = 1p;
units = “A”;
access = I;
endnature
Predefined Conservative Disciplines
Discipline
Potential
Nature
electrical Voltage
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Flow
Access Units
Nature
V
Current I
V
Access Units
A
magnetic Magnetomotive MMF
force
thermal Temperature Temp
A·turn Flux
Phi
Wb
C
Power
Pwr
W
kinematic
(position)
kinematic
(velocity)
rotational
(phase)
rotational
(velocity)
Position
Pos
m
Force
F
n
Velocity
Vel
m/s
Force
F
n
Angle
Theta
rads
Torque
Tau
n/m
Angular
velocity
Omega rads/s Torque
Tau
n/m
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Analog Blocks
• A process that runs from beginning to end at every point in time
– No blocking
Resistive Periodic Pulse Source
module pport (out);
electrical out; output out;
parameter real r, period, tt, v0, v1;
integer q;
period
v1
v0
tt
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analog begin
@(timer(period/2)) q = !q;
V(out) <+ 2*transition(q ? V1 : v0, 0, tt)
+ I*I(out);
end
endmodule
Signals
• Signals: potentials and flows associated with nodes or
branches
– Signal values are determined by analog kernel
– Are correct upon entry to analog block
– Accounts for all contributors from all analog processes
– Value is independent of order of access
– Allows implicit formulas
– Values are affected using contribution operators
– All contributions to same signal at the same point in time sum
– Behave much differently from values in variables
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Conceptual Simulation Cycle
• Step 1: Update the value of all input (probed) signals
• Step 2: Evaluate all models at time t
• Step 3: Resolve the value of all output (sourced) signals
– Sum multiple contributions
• Step 4: Kirchhoff’s laws satisfied, if not return to step 1.
• Step 5: Advance time
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Signal Access on Nodes, Ports,
Branches
• To get (probe) values: use access function in expression
– x gets voltage between a and ground:
x = V(a)
– x gets voltage between a and b:
x = V(a,b)
– x gets current between a and ground:
x = I(a)
– x gets current between a and b:
x = I(a,b)
• To set (source) values: use access function as target in contribution
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– set voltage between a and ground to x:
V(a) <+ x
– set voltage between a and b to x:
V(a,b) <+ x
– set current between a and ground to x:
I(a) <+ x
– set current between a and b to x:
I(a,b) <+ x
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Advanced Conservative Modeling
• Advanced features for modeling conservative systems
– Explicit equations
– Behavioral models with complex topologies
– Ideal switches
– Out-of-context references
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The Contribution Operator – ‘<+’
• Accumulates potentials or flows to nodes, ports, and branches
• Order of contribution is not significant
module rlc (a, b);
electrical a, b;
parameter R = 1 exclude 0;
parameter C = 1;
parameter L = 1 exclude 0;
analog begin
I(a,b) <+ V(a,b) / R;
I(a,b) <+ C*ddt(V(a,b));
I(a,b) <+ idt(V(a,b) / L;
end
endmodule
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The Contribution Operator – ‘<+’
• Supports implicit equations
– Solves for x when x <+ f(x)
module diode (a, c);
electrical a, c;
parameter is = 1f from (0:inf);
parameter rs = 0 from [0:inf);
a
c
analog begin
I(a,c) <+ is * ($limexp((V(a,c) – rs * I(a,c) ) / $vt) – 1);
end
endmodule
Limiting
I(a,c) on both sides
Exponential
makes eqn implicit
(helps convergence)
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Branches
• Modeled behavior is associated with branches
• Branches are either defined explicitly or implicitly
– Explicitly defined branches are referred to as named branches
• Branch type is determined by how branch values are accessed
– If potential is set: it is a potential source branch
– If flow is set: it is a flow source branch
– If neither is set: it is a probe branch
– If potential is probed: it is a potential probe branch
– If flow is probed: it is a flow probe branch
– If both are set: it is a switch branch
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Source Branches
• Potential source branch
– A branch whose potential is assigned by contribution
f
– Has built-in potential source
+
–
– Has built-in potential and flow probes
+p
–
• Flow source branch
– A branch whose flow is assigned by contribution
– Has built-in flow source
– Has built-in potential and flow probes
• Cannot contribute both potential and flow
to a single branch
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f
+p
–
Example: Resistor and Conductor
• Resistor (potential source branch) module res (a, b);
+
–
electrical a, b;
parameter r = 1;
i
v=ri
• Conductor (flow source branch)
+
–
v
i=gv
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analog
V(a,b) <+ r*I(a,b);
endmodule
module cond (a, b);
electrical a, b;
parameter g = 1;
analog
I(a,b) <+ g*V(a,b);
endmodule
Probe Branches
• Probe branch
– A branch to which no contribution is made
• Potential probe branch
– A branch whose potential is used in an expression
– On open circuit
• Flow probe branch
+ p
– A branch whose flow is used in an expression
– A short circuit
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f
–
Example: Controlled Sources
module vcvs (p, n, ps, ns);
electrical p, n, ps, ns;
output p, n; input ps, ns;
parameter gain = 1;
parameter gain = 1;
analog
V(p,n) <+ gain*V(ps,ns);
endmodule
analog
I(p,n) <+ gain*V(ps,ns);
endmodule
module ccvs (p, n, ps, ns);
electrical p, n, ps, ns;
output p, n; input ps, ns;
module cccs (p, n, ps, ns);
electrical p, n, ps, ns;
output p, n; input ps, ns;
parameter gain = 1;
analog
V(p,n) <+ gain*I(ps,ns);
endmodule
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module vccs (p, n, ps, ns);
electrical p, n, ps, ns;
output p, n; input ps, ns;
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parameter gain = 1;
analog
I(p,n) <+ gain*I(ps,ns);
endmodule
Named Branches
• Named branches are explicitly declared
– Useful when defining distinct parallel potential branches
module rlc (a, b);
electrical a, b;
parameter R = 1, C = 1, L= 1;
branch (a, b) res, cap, ind;
analog begin
V(res) <+ R*I(res);
I(cap) <+ C*ddt(V(cap));
V(ind) <+ L*ddt(I(ind));
end
endmodule
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Switch Branches
• A branch whose potential is occasionally, but not always,
assigned by contribution
• Switches between built-in potential and flow sources
• Has built-in potential and flow probes
f
+ p
–
+
–
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Hysteretic Relay
module relay (pout, nout, pin, nin);
voltage pout, nout, pin, nin;
input pin, nin; output pout, nout;
parameter real thresh = 0, hyst = 0;
real offset;
analog begin
@(cross(V(pin,nin) – thresh – offset, +1))
offset = –hyst;
@(cross(V(pin,nin) – thresh – offset, –1))
offset = hyst;
if (V(pin,nin) – thresh – offset > 0)
V(pout, nout) <+ 0;
end
endmodule
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Switch Branch
Formulating Equations for Simulation
• Natural to use either MNA or STA
• For STA
– Potential and flow for each branch become unknowns
– Each branch relation becomes an equation
• For MNA
– Unknowns include each node potential and the flow for each
potential branch, flow probe, and switch branch
– Equations include the total flow contributions into each node, along
with branch relations for each potential branch, flow probe, and
switch branch
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Tolerancing
• Unknowns and residues are always associated with natures
– Natures contain tolerancs
• STA example: consider I(cap) <+ c*ddt(V(cap))
– Unknowns: I(cap) a current, V(cap) a voltage
– Residue: I(cap) a current
• MNA example: consider I(cap) <+ c*ddt(V(cap))
– Unknowns: V(cap) a voltage
– Residue: I(cap) a current
• This is an advantage that Verilog-AMS has over VHDL-AMS
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Mathematical Functions and Operators
• User defined functions
• Standard mathematical functions
– Std math, logs, trig, hyperbolics
• Random numbers
– Uniform, Gaussian, exponential, Poisson, chi-squared, students-T,
Erlang
• Analog operators
– Derivative, integral, absdelay
• Analog filters
– Transition, slew, Laplace, z
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Analog Operators
• Differentiator: ddt()
– Time derivative of its argument
• Integrator: idt()
– Time integral of its argument
– Optional initial condition
• Circular integrator: idtmod()
– Time integral of its argument passed through modulus operation
• Time delay: absdelay()
– Delayed version of its argument
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VCO
VCO
module vco (out, in);
voltage out, in;
Circular Integrator
parameter k = 1;
real phase, freq;
analog begin
freq = k*V(in);
phase = idtmod(freq, 0, 1);
V(out) <+ cos(2*`M_PI*phase);
bound_step(1/(10*freq));
end
endmodule
Analog Filters
• Transition filter
– Converts piecewise constant signals to piecewise linear signals
• Slew filter
– Bounds the rate-of-change of signal at output
• Laplace filters
– Lumped linear continuous-time filter functions with user specified
poles and zeros
• Z filters
– Linear discrete-time filter functions with user specified poles and
zeros
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Transition Filter
• Filters piecewise continuous waveforms to piecewise linear
– Avoids simulation problems caused by discontinuous waveforms
– Adds finite rise and fall time
– Can add delay
• Avoid smoothly varying inputs
– Use slew filter instead
In
Out = transition( In, td, tt )
td
Out
tt
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Example: D Flip-Flop
D- Flip-Flop
module dff (q, d, clk);
voltage q, d, clk;
input clk, d; output q;
parameter real td=0 from [0:inf), tt=0 from [0:inf);
parameter integer dir=1 from [-1:1] exclude 0;
parameter real Vdd=5 from (0:inf);
integer state;
analog begin
@cross(V(clk) – Vdd/2, dir)
state = (V(d) > Vdd/2);
V(q) <+ transition(state*Vdd, td, tt);
end
endmodule
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Transition
Event-Driven Modeling
• @ blocks
– Blocks of code executed upon an event
• Event types
Name
Generates events …
cross()
timer()
initial_step
final_step
At analog signal crossings
Periodically or at specific times
At beginning of simulation
At end of simulation
• Time of the Last Zero Crossing; last_crossing()
Example: Sampler
Sampler
module sampler (out, in);
voltage out, in;
output out; input in;
parameter Tstart = 0;
parameter T = 1 from (0:inf);
parameter tt = T/10 from [0:T];
real hold;
State Variable
analog begin
@(initial_step or timer(Tstart, T))
hold = V(in);
V(out) <+ transition(hold, 0, tt);
end
endmodule
Event
Block
Cross Event Operator
cross( expr, direction, time-tolerance, expr-tolerance)
• Generates event when expr crosses 0 in specified direction
• Timepoint is placed just after the crossing within tolerances
• To know exact time of crossing,
use last_crossing()
Actual cross
Time point
Expr-Tol
Threshold
Time-Tol
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Example: Phase/Frequency Detector
module pfd_cp (out, ref, vco);
current out; voltage ref, vco;
output out; input ref, vco;
parameter Iout = 100u;
integer state;
analog begin
@(cross(V(ref)), +1)
if (state > –1) state = state – 1;
@(cross(V(vco)), +1)
if (state < 1) state = state + 1;
I(out) <+ transition(Iout*state);
end
endmodule
Event
Blocks
Example: Record Zero Crossing Times
module zero_crossings (in);
voltage in; input in;
parameter integer dir=1 from [-1:1] exclude 0;
integer fp; real last;
analog begin
@(initial_step)
fp = $fopen( “zero-crossings”);
last = $last_crossing(V(in), dir);
Record time
@(cross(V(in), dir))
of crossing
$fstrobe( fp, “%0.10e”, last);
@(final_step)
$fclose(fp);
end
endmodule
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Looping and Conditional Statements
• Verilog-A provides a complete set of loops and conditionals
– if / else: binary conditional
– case: n-ary conditional
– repeat: repeat a fixed number of times
– while: repeat until false
– for: repeat until false with initialization and incrementing
– generate: repeat until false with initialization and incrementing
– generate statements are being out-dated (replaced with for loop with
genvar index)
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Restrictions for Analog Operators &
Filters
• All of these statement place restrictions on the use of analog
operators and filters
– You must not use operators and filters in body of statement
– Analog operators and filters maintain internal state that is corrupted
when in a loop or conditional
• There are three exceptions
– Okay in if statement if conditional is constant expression
– Okay in for loop if index variable is genvar type
– Okay in generate statement
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Simulator Interface Functions
• Functions that communicate with the simulator
– analysis()
– discontinuity()
– Used to indicate that model is discontinuous at current point
– $abstime, $temperature, $vt, $vt()
– Returns time, temperature, or thermal voltage
– Small-signal stimulus functions
– ac_stim(), white_noise, flicker_noise, noise_table
– bound_step()
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Analysis Function
• Indicates whether analysis being run matches specified criteria
“ac”
.ac analysis
“dc”
.op or .dc analysis
“noise”
.noise analysis.
“tran”
.tran analysis.
“ic”
The initial-condition analysis that
precedes a transient analysis.
“static”
matches “dc” or “ic”
“nodeset”
The phase during an equilibrium point
calculation where nodesets are forced.
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Example: Capacitor with Initial Condition
module cap (a, b);
electrical a, b;
parameter real c=0, ic=0;
analog begin
if (analysis("ic"))
V(a,b) <+ ic;
else
I(a,b) <+ ddt(c*V(a,b));
end
endmodule
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Small-Signal Stimulus Functions
• Used to model stimulus on small-signal analyses (AC, noise)
– ac_stim()
– Active only during AC analyses
– white_noise()
– Noise constant with frequency, only active in noise analyses
– flicker_noise()
– Noise inversely proportional to frequency
– noise_table()
– Table model determines noise amplitude versus frequency
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Example: Noisy Diode
module diode (a, c);
electrical a, c;
branch (a, c) diode, cap;
parameter real is=1e–14, rs=0, tf=0, cjo=0, phi=0.7;
parameter real kf=0, af=1, ef=1;
analog begin
I(diode) <+ is*($limexp(V(diode)/$vt) – 1);
I(cap) <+ ddt(tf*I(diode) - 2*cjo*sqrt(phi * (phi * V(diode)));
I(diode) <+ white_noise( 2 * `P_Q * I(diode) );
I(diode) <+ flicker_noise( kf * pow(abs(I(diode)), af), ef);
end
endmodule
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Bound Step
• bound_step() places bound on the timestep
– Limits timestep
– Does not force point at any particular time
• Useful for autonomous circuits with smooth output waveforms
– Sinusoidal sources
– Oscillators and VCOs
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Example: Resistive RF Source
+–
module port (p, m);
voltage p, m;
parameter real r=50, dc=0, mag=0, ampl=0, freq=0, phase=0;
analog begin
V(p,m) <+ 2*dc – r*I(p,m);
V(p,m) <+ 2*ac_stim(mag);
V(p,m) <+ white_noise(4*`P_K*r*$temperature);
if (analysis(“tran”))
V(p,m) <+ 2*ampl*cos(2*`M_PI*freq*$abstime+phase);
bound_step(0.1 / freq);
end
endmodule
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Mixed Signal Domains
• There are two types of “domains” in Verilog-AMS
– Discrete - used to describe digital circuits
– Continuous - used to describe analog circuit
• It is used in partitioning analog from digital and determines
which solver (analog or digital) is used in solving its behavior
• The auto insertion of connect modules (IE’s) done directly in the
simulator uses this partitioning
• All analog and mixed signal modules require that ports and
nodes associated with behavioral code have a discipline
declared for them
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Mixed Signal Interaction
• In general, digital behavior is defined in the initial/always blocks
and analog in the analog block.
– All three types of blocks can appear in the same module.
– There can only be one analog block but many digital blocks.
• Read operations of continuous-time and discrete-time signals
are allowed from either context.
• Continuous-time signals only written from within analog context.
• Discrete-time signals only written outside of an analog context.
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Analog/Digital Interaction (2)
• Analog Signal / Variable Appearing in Digital Expression
...
reg clock;
real r;
electrical x;
always @(posedge clock)
begin
r = V(x);
end
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Analog/Digital Interaction (3)
• Digital Signal / Variable Appearing in Analog Expression
reg d;
electrical x;
analog begin
if (d === 0)
V(x) <+ 0.0;
else
V(x) <+ 3.0;
end
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Analog/Digital Interaction (4)
• Analog Event Appearing in Digital Event Control
electrical x;
reg d;
integer i;
always @(cross(V(x) - 4.5, 1))
begin
i = d;
end
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Analog/Digital Interaction (5)
• Digital Event Appearing in an Analog Event Control
real r;
reg d;
electrical x, y;
analog begin
@(posedge d)
r = V(x);
end
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Mixed Signal Modules
• Not just Verilog-D plus Verilog-A: True Mixed Signal blocks
• Can result in designs free of connect elements (IE’s)
• Mixed Signal blocks can be
– all behavioral, all structural, or mixed
– use full capability of both Verilog-D and Verilog-A
– have digital and analog sections interact by sharing data and
controlling each other’s events
• Allows for event driven modeling of analog blocks
• Verilog-D extended to support real value nets (wreal)
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Example - Sample and Hold
module samplehold (inSig, trigger, holdSig);
input inSig, trigger; output holdSig;
electrical inSig, holdSig; logic trigger;
parameter real Rout=1;
real vhold;
analog begin
// A digital event to which analog is made sensitive to:
@(posedge(trigger)) vhold = V(inSig);
// Drive output with held voltage and series resistance:
I(holdSig) <+ (V(holdSig)–vhold)/Rout;
end
endmodule
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The Mixed-Signal Synchronization Cycle
• Analog solver understands backstepping, but digital doesn’t
• Analog step always preceeds digital step
• When a digital simulation hits a D2A event, the analog solver
backsteps to the point of the event
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How to model the D-to-A Interface
General
• If a digital signal changes the analog behavior in any way, the
use of the transition function is strongly recommended
– Rise/fall times will otherwise equal the current analog timestep size
– If the step causes a convergence problem, analog simulation may
fail (since decreasing timestep size won’t help convergence)
• If using the digital value (not the event) in the analog block,
then every change of this value will cause an analog time step
– When digital signal changes, the analog sees the former state of the
signal, then recomputes the point with the new value of the signal
– If digital signal goes to X or Z, analog simulation immediately fails
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How to model the D-to-A Interface
Using a digital event to trigger analog behavior
• D2A Event at p4 causes analog simulation to backstep and then
step to the point of the event
tA
1
p5
p1
3
Induced
Analog
Backstep
tD
p3
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4
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p2
pn
analog simulation
time
digital simulation
time
How to model the A-to-D Interface
Using the analog value in the digital context
• Reading of analog values (accessing V(a) at p4 & p5) does not
force analog time steps
• The analog value is found by interpolation (analog simulation
always leads digital)
• The time point for the interpolation is the current digital time tick
converted to the analog real time
V(a)
t
A
t
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1
p
1
p3
p2
2
p
4
3
p
5
4
p6
How to model the A-to-D Interface
Triggering on an analog event in a digital context
• Analog event evaluated in digital context at largest digital time
tick less than or equal to analog time where event happened
• Reexecutes analog step up to point of new event, then
evaluates again at that timepoint with value updated
vth
V(a)
tA
tD
83
always @(cross(V(a)-vth,1))
1
p1
p2
3
2
p3
4
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5
pn
analog simulation
time
digital simulation
time
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