Download ECE 331 – Digital System Design

ECE 331 – Digital System Design
Electrical Characteristics of Logic Gates,
Circuit Design Considerations,
and
Programmable Logic Devices
Electrical Characteristics of Logic Gates
Electrical Characteristics
Representing Logic Values
Representing Logic Values
Voltage
supply voltage
VDD
Logic 1
V1,min
Undefined
V0,max
Logic 0
ground
VSS
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Noise Margin
Voltage
supply voltage
VDD
VOH
NMH = VOH - VIH
VIH
Undefined
VIL
NML = VIL - VOL
VOL
ground
VSS
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Voltage Levels
VIH
VOH
VIH
VOH
VIL
VOL
VIL
VOL
VOH, VOL, VIH, and VIL are specified in the data sheet
for the associated logic gate.
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Electrical Characteristics
Fan-out
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Fan-out


Fan-out is the number of gate inputs that can be
properly driven by a single gate output

Current must flow between logic gates

Current is limited by logic gate technology

Current limits fan-out
DC Fan-out is the fan-out when the output is at
steady-state.

Both high (1) and low (0) output states must be
considered when implementing logic circuit design

Select worst-case as limit
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Fan-out
N1
x
f
(a) Inverter that drives
To inputs of
n other inverters
n other inverters
Fanout is determined by taking the ratio of the output current (IOH, IOL)
of the driving device to the input current (IIH, IIL) of the load device(s).
The input and output currents are specified
in the data sheet of the associated logic gates.
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Electrical Characteristics
Interfacing between Logic Devices
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Interfacing between Logic Devices



Devices in the same logic family have the same
electrical characteristics.
Devices in different logic families often have
different electrical characteristics.
In order to interface between logic devices

Must consider the voltage levels of the driving
and load devices.

Must consider the current sourced and sunk
by the driving and load devices, respectively.
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Interfacing between Logic Devices


Voltage

The VOH of the driving device must be greater than
the VIH of the load device.

The VOL of the driving device must be less than the
VIL of the load device.

Noise Margin
Current

The driving device sources current for one or more
load devices.

Must consider the fan-out limit for the driving
device.
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Interfacing between Logic Devices

Noise Margin High (NMH)
NMH = VOH – VIH

Noise Margin Low (NML)
NML = VIL – VOL
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Electrical Characteristics
Example:
Determine the high and low noise margins when a
74LS00 NAND gate drives another 74LS00 NAND
gate.
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Example: Noise Margin


From the 74LS00 data sheet:

VOH_min = 2.7 V
VOL_max = 0.4 V

VIH_min = 2.0 V
VIL_max = 0.8 V
High Noise Margin


NMH = 2.7 V – 2.0 V = 0.7 V
Low Noise Margin

NML = 0.8 V – 0.4 V = 0.4 V
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Interfacing between Logic Devices

Low-state Fanout =
Floor[ IOL_max (driver) / IIL_max (load) ]

High-state Fanout =
Floor[ IOH_max (driver) / IIH_max (load) ]

Design the logic circuit based on the minimum
of the two fan-out limits.
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Interfacing between Logic Devices

Exceeding fanout limits leads to

Increase in output-low voltage (VOL)


Decrease in output-high voltage (VOH)


And possibly the wrong logic state
Increase in temperature


And possibly the wrong logic state
And possible destruction of the circuit / device
Increase in propagation delay
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Effect of Fan-out on Propagation
Delay
V f for n = 1
VDD
V f for n = 4
Gnd
0
Time
(c) Propagation times for different values of n
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Electrical Characteristics
Example:
Find the fan-out limit of a 74LS00 NAND gate
when driving one or more NAND gates on the
same chip.
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Example: Fanout Limit


From the 74LS00 data sheet:

IOH_max = - 0.4 mA
IOL_max = 8.0 mA

IIH_max = 20 mA
IIL_max = - 0.4 mA
Low-state fanout =


Floor[ 8.0 mA / 0.4 mA ] = 20
High-state fanout =

Floor[ 0.4 mA / 20 mA ] = 20
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Electrical Characteristics
Example:
Determine the noise margins and fanout limit for a
74LS00 NAND gate when driving one or more
74HC00 NAND gates.
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Example: Noise Margin

From the 74LS00 data sheet:


VIH_min = 3.15 V
VIL_max = 1.35 V
High Noise Margin


VOL_max = 0.4 V
From the 74HC00 data sheet:


VOH_min = 2.7 V
NMH = 2.7 V – 3.15 V = - 0.45 V
Low Noise Margin

NML = 1.35 V – 0.4 V = 0.95 V
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Example: Fanout Limit

From the 74LS00 data sheet:


IIH_max = IIL_max = +/- 1 mA
Low-state fanout =


IOL_max = 8.0 mA
From the 74HC00 data sheet:


IOH_max = - 0.4 mA
Floor[ 8.0 mA / 1 mA ] = 8000
High-state fanout =

Floor[ 0.4 mA / 1 mA ] = 400
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Programmable Logic Devices
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Programmable Logic Device


Programmable Logic Array (PLA)

Consists of a set of AND gates that feeds a
set of OR gates.

Realizes a Boolean expression using the
Sum-of-Products (SOP) form.
Programmable Array Logic (PAL)

Similar to the PLA

However, only the AND plane is
programmable.

The OR plane is fixed.
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Programmable Logic Array
x1
x2
x3
Programmable
connections
OR plane
P1
P2
P3
P4
AND plane
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1
f2
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Programmable Logic Array
x1
x2
x3
OR plane
P1
P2
P3
P4
AND plane
f1
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f2
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Programmable Array Logic
x1
x2
x3
P1
f1
P2
P3
P4
f2
AND plane
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Programmable Logic Devices


Complex Programmable Logic Device (CPLD)

Comprises multiple circuit blocks on a single
chip, with internal wiring resources to connect
the circuit blocks.

Each circuit block is similar to a PLA or PAL.
Field Programmable Gate Array (FPGA)

Supports implementation of relatively large
logic circuits.

Does not contain AND or OR planes.

Provides logic blocks for the implementation
of the required functions.
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PAL-like
block
PAL-like
block
I/O block
I/O block
CPLD
PAL-like
block
PAL-like
block
ECE 331 - Digital System Design
I/O block
I/O block
Interconnection wires
33
CPLD
PAL-like block (details not shown)
PAL-like block
D Q
D Q
D Q
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FPGA
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FPGA Logic Block
x1
0/1
0/1
f
0/1
0/1
x2
(a) Circuit for a two-input LUT
x1
x2
f1
0
0
1
1
0
1
0
1
1
0
0
1
(b) f 1 = x 1 x 2 + x 1 x 2
x1
1
0
f1
0
1
x2
(c) Storage cell contents in the LUT
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