Download 80-Tile Teraflop Network-On-Chip

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80-Tile Teraflop Network-OnChip
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Contents
• Overview of the chip
• Architecture
▫ Computational Core
▫ Mesh Network Router
▫ Power save features
• Performance
• Evaluation
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Overview of the chip
• Purpose: High speed floating point calculations
(research chip)
• Tile based
• NetworkOn-Chip
• Low power
consumption
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Computational core
The Processing Engine
inside the tile
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Mesh Network router
• 80 GB/s throughput
Mesochronous interface
• Data can be routed across 2 lanes
Overview of the crossbar router
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Mesh Network router
Interleaving
Routing
De-interleaving
Area reduction trough bit interleaving
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Power saving features
• Sleep transistors: reduce
standby leakage
• Body bias circuits: reduce
active leakage
• Controlled by special
instructions
Operating voltage: 0.7-1.2V
Operating frequency: 0-5.8GHz
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Performance
• Extreme amount of FLOPS/Watt
• Low voltage performance still impressive:
▫ 11W, 310 GFLOPS
Frequency
Voltage Power
Bisection Bandwidth
Performance
3.16GHz
0.95 V
62W
1.62 Terabits/s
1.01 Teraflops
5.1GHz
1.2 V
175W
2.61 Terabits/s
1.63 Teraflops
5.7GHz
1.35 V
265W
2.92 Terabits/s
1.81 Teraflops
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Evaluation
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Very scalable
Energy efficient
Heat spreading possible
Fault tolerant
Dynamic routing across mesh network
3d stacked memory very promising
• Not general purpose yet
• Communication with the outside world is hard
• Programming might be a problem
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End of presentation