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```Static (DC) Characteristics
of MOS Inverters
Prof. MacDonald
1
MOS Inverters
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Most fundamental circuit in MOS family
Represents the basic operation of all static gates
One input and one output
–
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Inverter Threshold Voltage - Vth
–
–
2
Output = ~Input
input voltage where output equals input
not the same as transistor threshold Vt
Voltage Transfer Characteristic (VTC) ideal
Vout
Vdd
infinite gain at threshold
zero gain
at all other
input voltages
3
Vth
Vdd
Vin
General Inverter Model
Vdd
+
-
output
input
When Input high, NFET turns on and we have a voltage dividing
resistor network consisting of the NFET (Low R) and Load (High R).
Consequently, the output will be dropped down to RL/(RL + RH).
Current will be constant (bad) and equal to Vdd/(RL + RH).
4
General Inverter Model
Vdd
Vdd
output
input
When Input Low, NFET turns off and capacitor is charged fully to Vdd.
No current runs through the load and no voltage drop exists across the
5
Voltage Transfer Characteristic (VTC)
Vout
Vout = Vin
Vdd
gain = -1
6
Vil
Vth
Vih
Vdd=Voh
Vin
Noise Margin – low gain region
Vout
low gain region
gain = -1
7
Vin
Noise Margin – high gain region
Vout
high gain region
Good design minimizes
high gain region
aka transition region.
gain = -1
8
Vin
Noise Margin
Vin
Vout
NMH=Voh-Vih
NMH
Voh
Vih
transition region
indeterminate
Vil
9
NML=VoL-ViL
NML
Vol
Single Source Noise Margin
Voh+Vn
Vol
?
+
Voh
Vol
?
Voh
?
Vol
?
Voh
Vn
If Vn is less than noise margin than the noise will
be attenuated each stage and will quickly disappear.
If Vn is greater than the noise margin, the noise will
result in voltages at the input that will be in the high
gain region and will be amplified through subsequent stages.
10
Vdd
output
Irl = Ids
input
I
Vdd
RL
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Vol
Voh=Vdd
Vout
Resistive Load Inverter – Voh and Vol
Voh
Voh = Vdd because when the input voltage
drops below Vt of the inverter, no current flows.
No current flow in turn means no voltage drop
across the load resistor and Vout = Vdd = Voh.
Vol
If the input is driven to Voh=Vdd then the transistor
is on and since Vgs > Vds it is also
in linear mode. The drain will be at Vol and the
gate will be at Voh.
1
Vdd − Vol
2
Ids = Ir = • K • 2 • (Vgs − Vt 0) • Vds − Vds =
2
R
[
12
1
Vol ≈ Vdd − Vt +
− 1 + K • Rl (Vdd − Vt )
KR
]
Vil
To determine noise margin we need Vil which is one of
two points where we have unity gain.
When input low, output high and NFET in saturation.
1
Vdd − Vout
2
Ids = Ir = • K • (Vgs − Vt 0) =
2
R
13
1
Vil = Vt +
KRl
Vih
When Vin = Vih, the output is at Vol and the NFET
is in the linear region.
1
Vdd − Vol
2
Ids = Ir = • K • 2 • (Vgs − Vt 0) • Vds − Vds =
2
R
[
14
8Vdd
1
Vih = Vt+
−
3kR kRl
]
1
Vdd − Vout
2
Ids = Ir = • K • (Vin − Vt 0) =
2
R
Vin = Vout = Vth
1
Vdd − Vth
2
• K • (Vth − Vt 0) =
2
R
Solve for Vth in quadratic equation.
Correct root should be between 0 and Vdd
15
Resistive Load Inverter – Static Power
P =V • I
Vdd − Vout
I ds = Ir =
R
Vdd − Vout
P = (50%) • Vdd •
R
16
Vout
kR=2V-1
kR=4V-1
kR=8V-1
17
Vin
Vgg
Vdd
output
Il = Id
Two power supplies needed
Vout = Vdd.
input
I
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Vol
Voh=Vdd
Vout
Vdd
Vdd
Il = Id
output
input
Load NFET is always on and
acts like a non-linear resistor.
Requires two types of NFETs.
I
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Vol
Voh=Vdd
Vout
Voh = Vdd
Vol ≈ 0
⎛ Kl ⎞
Vil = Vt 0 + ⎜ ⎟ • [Vout − Vdd + Vtload (Vout )]
⎝ Kd ⎠
Solve for Vth in quadratic equation.
Correct root should be between 0 and Vdd
20
CMOS Inverter
Vout
Vout=Vin-Vtp
Vout=Vtn
A
Vout=Vdd+Vtp
B
Vout=Vin-Vtn
C
D
E
21
Vin
CMOS Inverter
Vout
Ids
Vdd
22
Vin
CMOS Inverter – Noise Margin
Voh = Vdd
23
Vol = gnd
Vdd + Vto + kr • (2 • Vout + Vtn )
V ih =
1 + kr
2Vout + Vtp − Vdd + kr • Vtn
Vil =
1 + kr
1
Vtn +
(Vdd + Vtp)
k
r
Vth =
1
1+
kr
Layout of inverter – top view
n-well
W
W
24
Layout of inverter – top view
n-well
gate
vdd
I1
drain
I2
drain
source
input
gnd
source
I1
out
in
I2
25
CMOS Tri-state Inverter
~en
output
input
en
26
CMOS Inverters - Summary
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At normal input levels, little static power
What happens if input is floated?
Dynamic Power only during transitions
In transition region, short circuit current exists
Very good noise properties
Body effect is irrelevant as no stacked transistors
transconductance ratio determines Vth
```
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