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Packetized Broadband Correlator ASIAA, Institute of Astronomy and Astrophysics, Academia Sinica Taiwan Homin Jiang Mini CASPER Taiwan Workshop 2011, Taipei 1 Contents • • • • • • • • Concept of Packetized Correlator F Engine X Engine System Backend: Initialization, transmission, receiver SMA Specification Proof of Concept : Phase 1 Proof of Concept : Phase 2 Discussion 2 Correlator for Array • Many baselines. • 2 ways. – backplane bus (typical) or packetized • transmission thru high speed network. • ALMA, SMA -- backplane solution. • PCI , ISA, or other standard buses. • Resources concerned. ALMA solution or Japanese Solution. 3 Packetized Correlator Concept Or by regular Ethernet to every ROACH board Jason Manly 4 F Engine Inside Coarse Delay PFB FFT Fringe Rotate Corner Turn Pketize Quantiz Reorder X 5 F Engine Inside Coarse Delay PFB FFT Fringe Rotate Quantiz Corner Turn Pketize X Reorder 6 F Engine Inside Coarse Delay PFB FFT Fringe Rotate Corner Turn Pketize Quantiz Reorder X 7 X Engine Inside F DePack Buffer X Accum Borph 8 X Engine Inside F DePack Buffer X Accum Borph 9 System Backend : System Schematic Init ROACH PowerPC Linux BORPH FPGA Start Rx Display ROACH Server Computer ROACH 2 Start Tx ROACH n 10 System Backend Init Start Tx Start Rx Display • Software registers on ROACH FPGA addressable by BORPH on ROACH’s Power PC embedded Linux system. • Automated Python scripts for writing these registers. • “start TX” command begins dumping the data in shared BRAM of Xengine or Xvacc on separate UDP port or 10G port. • Receiver collects UDP packets, buffers and saves to disk. • Multiple files generated for storage,display and debugging. 11 System Backend: Init Init Start Tx Start Rx Display • Python script run on server computer. • Program the specified bof file one by one on separate UDP port. • Tests F and X engine one Roach by one Roach. • Allows programming of any software register on the Roach FPGA by name. • Program the gains, accumulation, FFT shift schedule, equalization, etc. • Checking the timing, synchronization etc. • Checking the UDP, 10G communication. 12 System Backend: Transmit Init • • • • • Start Tx Start Rx Display Python script run on ROACH/Linux. Reads out data in X engine or X vacc BRAMs when full. Data is enclosed in a timestamped packet. Transmitted via UDP packet to server computer. Can go thru Ethernet or 10GbE port. 13 System Backend: Receiver Init Start Tx Start Rx Display • • • • Python script run on server computer. Receives packets, decodes header and appends to buffer. If header out of order, dumps as invalid. Generates 4 files: Miriad UV, info files(n_chans, integration length, gain etc), plot of last integration, raw data file. • Creates HDF5 file format. “is a data model, library, and file format for storing and managing data. It supports an unlimited variety of datatypes, and is designed for flexible and efficient I/O and for high volume and complex data.” 14 System Backend: Display Init Start Tx Start Rx Display 15 Draft Spec. of Broadband SMA Corr. • • • • • • • Bandwidth : 18 GHz Polarizations : 2 No. of Antenna : 8 Channel Resolution: 32768 channels over the full band :500KHz spectral resolution. FX configuration preferred Zoom in function ADC >= 10Gsps preferred 16 Proof of Concept SMA Broaddband Correlator-phase 0 iADC 1 Gsps ADC , 8 bits 0.5 GHz ROACH F Engine 0.5 GHz ROACH F Engine ROACH 10 GE Switch 64 ports X Engine ROACH X Engine Ethernet 17 Proof of Concept SMA Broaddband Correlator-phase 1 iADC 1 Gsps ADC , 8 bits 0.5 GHz ROACH 0.5 GHz F Engine 0.5 GHz ROACH 0.5 GHz F Engine ROACH 10 GE Switch 64 ports X Engine ROACH X Engine Ethernet 18 Proof of Concept SMA Broadband Correlator-phase 2 5G ADC, 5 Gsps ADC , 4 bits dmux 1:8, one polarization 2 GHz Decimation after PFB ROACH 2 GHz F Engine 2 GHz ROACH 2 GHz F Engine ROACH 10 GE Switch 64 ports X Engine ROACH X Engine Ethernet 19 Discussion • How to fit the 8x18GHz bandwidth in ROACH2 or ROACH3 ? • 5G ADC is not wide enough. • 10 G Ethernet transmission would be a bottom neck ? • The team keeps searching for higher data rate ADC. The IF will be complicated and expensive with 5G adc. • Decimation after PFB ? What is the drawback of decimation ? 20