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Architecture of the PIC18F452
Copyright University of Colorado, 2005
ASEN 4519/5519
Lecture #3
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Comments
• Questions?
• New students
– Must attend ITLL orientation to receive computer account
and after hours access
– Sign-up for orientation at the ITLL front desk
Copyright University of Colorado, 2005
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Lecture #3
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Overview
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•
•
•
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PIC18F452 block diagram
PIC18F452 Pin out
Ports and resources
QwikFlash board schematic
PIC18F451 memory management
Numbering systems
– Decimal, binary, octal and hexadecimal
• RAM layout
• Special function registers
• Addressing modes
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PIC18Fx52
PIC18Fx52
block
diagram
EEPROM
256
RAM
1536
FLASH
32K
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PIC 18F452 Pin diagram
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The PIC18F452
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•
The PIC18F452 has 5 ports (A-E)
Each port has 3 associated 8-bit registers
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TRISx.bit defines the direction of bit in port x
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–
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TRISx.bit = 0 sets port x bit to be output
TRISx.bit =1 sets port x bit to be input
PORTx.bit is used to read the value of bit on port x
LATx.bit is used to set the value of bit on port x
A register is a reserved memory location in RAM
For example TRISA is at memory location 0xF92
If the value of TRISA = 00101101 then
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–
TRISA.0 =1 so port A pin 0 (RA0) is an input (pin #2)
TRISA.1 = 0 so port A pin 1 (RA1) is an output (pin #3)
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The PORTS
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Port A – 7 bit wide bidirectional port
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Port B – 8 bit wide bidirectional port with weak pull-up resistors
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Resources: Timers 1-3, capture compare, SPI, I2C, UART
Port D – 8 bit wide bidirectional port
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Resources: Interrupts, alt CCP2
Port C – 8 bit wide bidirectional port
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Resources: Timer0, Low voltage detect, ADC
Resources: Parallel slave port data
Port E – 3 bit wide bidirectional port
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Resources: Parallel slave port control
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PORT A
Bit #
Pin #
0
2
RA0, AN0
Digital I/O, analog input 0
1
3
RA1, AN1
Digital I/O, analog input 1
2
4
RA2, AN2, VREF-
Digital I/O, analog input 2, analog Vref -
3
5
RA3, AN3, VREF+
Digital I/O, analog input 3, analog Vref +
4
6
RA4, TOCKI
Digital I/O (open drain), timer0 clock in
5
7
RA5, AN4, SS,
LVDIN
Digital I/O, analog input 4, slave select
input (synchronous serial port), low
voltage detect
6
14
RA6, OCS2, CLK0
Digital I/O, OSC2, clock output
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Name
Function
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PORT B
Bit #
Pin #
0
33
RB0, INT0
Digital I/O, external interrupt 0
1
34
RB1, INT1
Digital I/O, external interrupt 1
2
35
RB2, INT2
Digital I/O, external interrupt 2
3
36
RB3, CCP2
Digital I/O, capture 2 input, compare 2 output,
pulse width modulation with CCP2MX bit
disabled
4
37
RB4
Digital I/O, IOC
5
38
RB51, PGM
Digital I/O, IOC, low voltage ICSP programming
6
39
RB6, PGC
Digital I/O, IOC, serial programming clock
7
40
RB7, PGD
Digital I/O, IOC, serial programming data
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Name
Function
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PORT C
Bit #
Pin #
0
15
RC0, T1OSO,
T1CKI
Digital I/O, timer1 oscillator out, timer1
clock in
1
16
RC1, T1OSI, CCP2
Digital I/O, timer1 oscillator in, capture 2
in, compare 2 out, pulse width modulator
out with CCP2MX bit enabled
2
17
RC2, CCP1
Digital I/O, capture 1 in, compare 2 out,
pulse width modulator out
3
18
RC3, SCK, SCL
Digital I/O, synchronous serial clock for
I2C and SPI
4
23
RC4, SDI, SDA
Digital I/O, SPI data input or I2C data I/O
5
24
RC5, SDO
Digital I/O, SPI data output
6
25
RC6, TX, CK
Digital I/O, USART asynchronous TX,
USART synchronous clock
7
26
RC7, TX, DT
Digital I/O, USART asynchronous RX,
USART synchronous data
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Name
Function
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PORT D
Bit #
Pin #
0
19
RD0, PSP0
Digital I/O, parallel slave port bit 0
1
20
RD1, PSP1
Digital I/O, parallel slave port bit 1
2
21
RD2, PSP2
Digital I/O, parallel slave port bit 2
3
22
RD3, PSP3
Digital I/O, parallel slave port bit 3
4
27
RD4, PSP4
Digital I/O, parallel slave port bit 4
5
28
RD5, PSP5
Digital I/O, parallel slave port bit 5
6
29
RC6, PSP6
Digital I/O, parallel slave port bit 6
7
30
RC6, PSP7
Digital I/O, parallel slave port bit 7
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Name
Function
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PORT E
Bit #
Pin #
0
8
RE0, AN5, RD
Digital I/O, analog input 5,
parallel slave port read
1
9
RE1, AN6, WR
Digital I/O, analog input 6,
parallel slave port write
2
10
RE2, AN7, CS
Digital I/O, analog input 7,
parallel slave port chip select
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Lecture #3
Function
12
Resources
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Timer0
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–
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Timer1
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8 or 16 bit timer
8 bit prescaler
Internal or external clock
Interrupt on overflow
16 bit time or counter
Internal or external clock
Interrupt on overflow
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–
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8 bit timer
8 bit period register (PR2)
Prescaler
Postscaler
Intrrupt on TMR2=PR2
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10 bit resolution
8 channels multiplex to a single
ADC
Serial interfacing
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10 bit resolution
Analog to digital converter (ADC)
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16 bit capture/compare
Pulse width modulation (PWM)
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16 bit timer or counter
CCP1 & CCP2
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Timer2
–
–
–
–
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Timer3
I2C, SPI, UART
Interrupts
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Timer, UART, SPI, I2C, ADC, …
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PIC
Qwikflash
board
SPI DAC
RS-232
Potentiometer (AN4)
Red LEDs
Temperature sensor (AN0)
LCD w/
Nibble interface
Pushbutton switch (RD3)
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Rotary pulse generator
(RD1,0)
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PIC Architecture
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Harvard architecture
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Operand address bus
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8 bits wide
Program address bus
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12 bits wide
2^12 = 4096
15 bits wide
2^15 = 32768
Instruction bus
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Operand
Address
Program
Address
12 bits
15 bits
Data bus
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Separate program and data
bus
Supports pipelining
Fetch next instruction while
executing current instruction
Program
Memory
CPU
Instruction
16 bits
Data
Operand
Memory
(SFR &
RAM)
8 bits
16 bits wide
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Number systems I
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Basic numbering systems
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Decimal system
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Base 10 (10 digits, 0-9)
Number 467 = 4*100 + 6*10 + 7*1
Binary system
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Base X (X digits)
number ABC = A*X^2 + B*X^1 + C*X^0
Nth place represents X^n
Base 2 (2 digits, 0 &1, ON & OFF, TRUE & FALSE)
Number 1101 = 1*2^3 + 1*2^2 + 0*2^1 + 1*2^0 = 8 + 4 + 0 + 1 = 1310
Octal system
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Base 8 (8 digits, 0-7)
Number 467 = 4*8^2 + 6*8^1 + 7*8^0 = 4*64 + 6*8 + 7 = 31110
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Number systems II
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Hexadecimal system
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Base 16 (17 digits, 0-9 & A-F)
Number 467 = 4*16^2 + 6*16^1 + 7*16^0 = 4*256 + 6*16 + 7 = 112710
Relationship between number systems
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1 octal digit = 3 binary digits
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1 hexadecimal digit = 4 binary digits
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111= 7
1111 = F
Notation
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Number are assumed to be in decimal unless otherwise specified
0x76 or H’76’ refers to a hexadecimal number
O’76’ refers to an octal number
B’01001100’ refers to a binary number
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Relationship between numbers
Decimal
Binary
Octal
Hexadecimal
0
0000
0
0
1
0001
1
1
2
0010
2
2
3
0011
3
3
4
0100
4
4
5
0101
5
5
6
0110
6
6
7
0111
7
7
8
1000
10
8
9
1001
11
9
10
1010
12
A
11
1011
13
B
12
1100
14
C
13
1101
15
D
14
1110
16
E
15
1111
17
F
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Binary numbering language
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Bit – a binary digit (0 or 1)
Nibble or nybble – a group of 4 bits. Corresponds to a single
hexadecimal digit
Byte – a group of 8 bits. It can be represented by two hexadecimal
digits.
Word - a group of 16 bits
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RAM layout
0x000
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12 bit address space
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–
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•
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0x080
0x100
2^12 = 4096 bytes
Only 1536 +128 are used
Bank 1
RAM divided into 16 banks
each 256 bytes large
PIC18F452 uses 6 banks for
general purpose registers
(GPR) and 128 bits for special
functions registers (SFR).
The SFR are located at the top
of ram
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•
Bank 0
GPR
0x200
Bank 2
GPR
0x300
GPR
Bank 3
0x400
GPR
Bank 4
0x500
GPR
Bank 5
0x600
Addresses 0xF80 to 0xFFF
UNUSED
The lowest 128 bits of RAM
are called access RAM
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Addresses 0x000 to 0x080
Banks 6-14 and the lower
half of bank 15 are unused
0xF00
Bank 15
0xF80
0xFFF
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Access RAM
GPR
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SFR
20
Special Function Registers
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PIC Addressing modes
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Literal addressing
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For moving constant values
Eg: movlw 0x23 – move the literal value 23 (hex) into the working register
Direct Addressing
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–
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For moving variables (eg: movwf COUNT – move the value of the working into
variable COUNT.
Access bank direct (0x000 to 0x07F)
Bank direct (0xB00 to 0xB7F)
•
•
Requires correctly initializing Bank Select Register (BSR)
Indirect Addressing
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Variable pointers
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Useful for numbers larger than one byte
Utilizes registers
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FSR0, FSR1, FSR2 (FSRx, x=0,1,2)
INDEFx, POSTDECx, POSTINCx, PREINCx, PLUSWx, where x=0,1,2 and
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Homework
LAB WEDNESDAY 31-AUG-05
• ITLL Electronics shop (2-3pm)
• Build your board
• Read
– Lab handout
– Peatman Chapter 4
– Peartman Appendix A1
LAB FRIDAY 02-SEP-05
• ITLL Electronics shop (2-4pm)
Copyright University of Colorado, 2005
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Lecture #3
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