Download Basics of Verilog-AMS

ECEN 468
Advanced Logic Design
L e c t u r e 3 1 : B a s i c s o f Ve r i l og - A M S
ECEN 468 Lecture 31
Introduction
v Verilog-AMS is a modeling language for mixed-signal systems
v Primarily for simulation of mixed-signal systems
v In general, synthesis is not supported
Verilog-AMS
Verilog-HDL
Verilog-A
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Analog vs. Digital
Digital
Analog discrete event
Analog continuous signal
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Architecture of Mixed-Signal Simulators
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APPLICATIONS OF VERILOG-AMS
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Component Modeling
v More built-in models than SPICE
v Basic components: resistors, capacitors, inductors…
v Diodes, BJTs, MOSFETs…
v Functional blocks: data converters, de/modulators, filters…
v Sensors, actuators, transducers…
v Logic gates, latches, registers…
v Testbench components: sources, monitors…
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Simulation Acceleration
v For circuit simulation
v Describe non-critical parts with behavioral models
v Behavioral models simulates much faster than transistor level
models
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Other Applications
v Mixed-signal design
v Top-down design
v Testbenches
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Modeling Resistor
v Natures: physical signal types
v Discipline: a collection of related natures
v Electrical discipline consists of voltages
and currents
module resistor(p, n);
parameter real r=0; //Ohms v “analog” introduces an analog process, to
inout p, n;
describe continuous time behavior
electrical p, n;
v Contribution statement
v Contribution operator ‘<+’
analog
v Implicit or unnamed branch (p, n), its two
V(p,n) <+ r*I(p,n);
endpoints must belong to equivalent
endmodule
disciplines
v Access functions: V, I
//Linear resistor
‘include “disciplines.vams”
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Modeling Conductor
//Linear conductor
‘include “disciplines.vams”
module conductor(p, n);
parameter real g=0; //Siemens
inout p, n;
electrical p, n;
analog
I(p,n) <+ g*V(p,n);
endmodule
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Capacitor
//Linear capacitor
‘include “disciplines.vams”
module capacitor(p, n);
parameter real c=0; // F
inout p, n;
electrical p, n;
analog
I(p,n) <+ c*ddt(V(p,n));
endmodule
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Inductor
//Linear inductor
‘include “disciplines.vams”
module inductor(p, n);
parameter real L=0; // H
inout p, n;
electrical p, n;
analog
V(p,n) <+ L*ddt(I(p,n));
endmodule
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Voltage Source
//DC voltage source
‘include “disciplines.vams”
module vsrc(p, n);
parameter real dc=0; // V
inout p, n;
electrical p, n;
analog
V(p,n) <+ dc;
endmodule
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Current Source
//DC current source
‘include “disciplines.vams”
module isrc(p, n);
parameter real dc=0; // A
inout p, n;
electrical p, n;
analog
I(p,n) <+ dc;
endmodule
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A Simple Circuit
‘include “disciplines.vams”
‘include “vsrc.vams”
‘include “resistor.vams”
module smpl_ckt;
electrical n;
ground gnd;
vsrc #(.dc(1)) V1(n, gnd);
resistor #(.r(1k)) R1(n, gnd);
endmodule
•  Two ports cannot be directly
connected, must via a common
electrical node
•  Every circuit has one node
designated as the ground or
reference node
•  Syntax of instantiation
• 
• 
• 
• 
Module name
Parameter list (optional)
Instance name (optional)
Node list
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Parameter List and Node List
Parameter list:
#(.p1(v1), .p2(v2))
#(.p2(v2), .p1(v1))
#(v1, v2)
#(, v2)
Node list:
(.p1(n1), .p2(n2))
(.p2(n2), .p1(n1))
(n1, n2)
(, n2)
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Reference Node
v The ground node always exists
v Its potential is zero
v V(p) means voltage from node p to the ground node
v I(p) means current from node p to the ground node
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Nature
v A nature is used to describe basic physical quantity
nature Current
units = “A”;
access = I;
abstol = 1e-12;
endnature
Absolute tolerance: the largest amount can
be negligible
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Discipline
discipline electrical
potential Voltage;
flow Current;
enddiscipline
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Derived Natures
nature HighVoltage: Voltage
abstol = 1;
endnature
nature HighCurrent: Current
abstol = 1e-3;
endnature
electrical lv;
hv_electrical hv;
analog
I(hv, lv) <+ g*V(hv,lv);
discipline hv_electrical
potential HighVoltage;
flow HighCurrent;
enddiscipline
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Range Limits
parameter real is=10f from (0:inf);
parameter real tf=0 from [0:inf);
parameter real cj=0 from (-inf:0];
parameter real phi=0.7 exclude 0;
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