Download EB63 - MT9M024 NanoVesta Head Board


MT9M024 NanoVesta Head Board
User’s Guide
May 2012
Revision: EB63_01.1

MT9M024 NanoVesta Head Board
User’s Guide
Introduction
The NanoVesta Head Board comprises a compact, low cost, high dynamic range (HDR) image sensor, lens and
lens housing with adjustable focus, that can bolt directly onto the Lattice HDR-60 Base Board. Both the NanoVesta
and HDR-60 boards have been designed to work together as part of the Lattice HDR-60 Video Camera Development Kit. The NanoVesta Head Board is designed to use the Aptina MT9M024 1/3-inch CMOS Digital Image Sensors which feature:
• Superior low-light performance
• HD video (720p60)
• Selectable linear or high dynamic range capture
• Selectable video or single frame modes
• On-chip auto exposure and statistics engine
• Parallel and serial output
• Auto black level calibration
• Context switching
Read more about the image sensor specifications in the Aptina MT9M024 data sheet.
Important: This document (including the schematics in Appendix A) describes the Lattice NanoVesta Head Board
marked as Revision 2. This marking can be seen on the top layer silkscreen of the printed circuit board, below the
outside perimeter of the lens holder.
Features
Key features of the NanoVesta Head Board include:
• Aptina MT9M024 1/3-inch CMOS Digital Image Sensor
• Lens: F/1.59, <7% distortion, with minimized flare, halo, and ghosting
• Lens holder with adjustable focus
• HiSPi and parallel signal connections to the HDR-60 Base Board
• Selectable 1.8V or 2.8V sensor VDDIO
• Selectable on-board 27.000 MHz MEMs oscillator, or HDR-60 Base Board oscillator
• 2.8V, VDDIO, 1.8V, 0.4V voltages are generated from the HDR-60 Base Board 5V
• Power status LEDs with one user-defined LED
General Description
The NanoVesta Head Board has been designed for use on the HDR-60 Base Board as part of the HDR-60 Video
Camera Development Kit. The NanoVesta Head Board contains the camera sensor portion of the kit, while the
HDR-60 Base Board contains the follow-on video camera image processing system. See the HDR-60 Base Board
User’s Guide for more information concerning that board.
Initial Setup and Handling
The following is recommended reading prior to removing the evaluation board from the static shielding bag and
may or may not apply to your particular use of the board.
CAUTION: The devices on the boards can be damaged by improper handling.
2
MT9M024 NanoVesta Head Board
User’s Guide
The devices on the evaluation boards contain fairly robust ESD (Electro Static Discharge) protection structures
within them, able to withstand typical static discharges (see the “Human Body Model” specification for an example
of ESD characterization requirements). Even so, the devices are static-sensitive to conditions that exceed their
designed-in protection. For example: higher static voltages, as well as lower voltages with lower series resistance
or larger capacitance than the respective ESD specifications require can potentially damage or degrade the
devices on the evaluation board.
As such, it is recommended that you wear an approved and functioning grounded wrist strap at all times while handling the evaluation boards when they are removed from the static shielding bag. If you will not be using the boards
for a while, it is best to put them back in the static shielding bag. Please save the static shielding bag and packing
box for future storage of the boards when they are not in use.
When reaching for the boards, it is recommended that you first touch the outside shield portion of the J11 BNC
connector on the HDR-60 Base Board. If the NanoVesta Head Board is not installed on the HDR-60 Base Board,
then when reaching for the NanoVesta board, it is recommended that you first touch the outside edge of the mounting holes on the NanoVesta board. This will neutralize any static voltage difference between your body and the
board prior to any contact with signal I/O.
CAUTION: To minimize the possibility of ESD damage, the first and last electrical connection to the board, should
be from test equipment chassis ground to the J11 BNC shield GND on the HDR-60 Base Board.
Before connecting signals or power to the board, attach a cable from chassis ground on grounded test equipment
to the J11 BNC shield GND on the HDR-60 Base Board. Connecting the board ground to test equipment chassis
ground will decrease the risk of ESD damage to the I/O on the board as the initial connections to the board are
made. Likewise, when unplugging cables from the evaluation board, the last connection unplugged should be the
chassis GND connection to the evaluation board GND. If you have a signal source that is floating with respect to
chassis GND, attempt to neutralize any static charge on that signal source prior to attaching it to the evaluation
board.
If you are holding or carrying the board while it is not in a static shielding bag, please keep one finger on the J11
BNC shield GND on the HDR-60 Base Board. If carrying the NanoVesta board alone, keep one finger one of the
mounting holes. This will keep the board at the same voltage potential as your body until you can pick up the static
shielding bag and put the board back in it.
Electrical, Mechanical, and Environmental Specifications
The nominal board dimensions are 42mm x 42mm (1.654” x 1.654”). Additional mechanical board dimension information is included on the mechanical drawing shown in Appendix A, Figure 6. On the physical board itself, connectors include pin 1 indictors as either an arrow, or triangle point near pin 1 on the outer layer silk screen. The
environmental specifications are as follows:
• Operating temperature: 0°C to 55°C
• Storage temperature: -40°C to 75°C
• Humidity: <95% without condensation
3
MT9M024 NanoVesta Head Board
User’s Guide
Functional Description
Figure 1. NanoVesta Head Board Revision 2
Voltage Regulators
The NanoVesta Head Board power is supplied by the 5V DC power applied at connectors J4 and J5, pins 1, 2, 39
and 40. The on-board linear voltage regulators then provide the necessary supply voltages to power the sensor:
2.8V, VDDIO, 1.8V, and 0.4V. LEDs D1, D2, and D3 will light up if their respective powers are active. The regulator
output voltages are set as shown in Table 1.
Table 1. NanoVesta Head Board Regulator Voltages
Supply
Voltage Regulator
Resistor Ratio
LED
5.0V
2.8V
On HDR-60 Base Board
—
D3
U4
R43/R45
D2
VDDIO
U3
R16/(R19+R20)
—
1.8V
U5
R44/R46
D1
0.4V
U2
R17/R18
—
Comment
5V arrives at J4 and J5
2.8V: Jumper on J3 (default)
1.8V: No jumper on J3
Each of the LT3025 regulators U2, U3, U4, and U5, are the linear low dropout voltage type that incorporate an
external resistor divider voltage feedback to divide down the regulator output voltage and compare it against an
internal reference voltage. The regulator then adjusts the output voltage higher or lower such that the resistor
divided voltage matches the internal reference. By doing this, each regulator output voltage remains at a constant
voltage value independent of the load it drives. Each regulator output voltage follows this equation:
VOUT = (1 + resistor ratio) x (regulator internal reference voltage)
See the LT3025 device data sheet for additional details about this device.
The VDDIO regulator output voltage can be set to 1.8V or 2.8V by removing or adding a shorting jumper on J3, as
shown in Table 1. With a jumper on J3, the voltage divider is set by R16 and R20 and this divider sets up a nominal
2.8V output voltage. When the shorting jumper on J3 is removed, the R19 resistor is placed in series with R20,
which then changes the resistor divider ratio, and this changes the VDDIO regulator output voltage to become 1.8V.
The default configuration is with the NanoVesta Head Board VDDIO set to 2.8V as shown in Figure 2.
4
MT9M024 NanoVesta Head Board
User’s Guide
Figure 2. NanoVesta Head Board Default Jumpers Diagram
Internal 27 MHz
J2
HDR-60 Base Board Oscillator
VDDIO (On = 2.8V, Off = 1.8V)
J3
MEMS Oscillator (Y1)
As shown in Figure 2, J2 is set such that the NanoVesta sensor will receive a clock input signal from the internal
27.000 MHz MEMS oscillator (Y1). The alternate position of J2 down will select the HDR-60 Base Board oscillator
for the NanoVesta sensor clock input.
HiSPi Connector (J5)
The Aptina MT9M024 (U1) can produce HiSPi sub-LVDS video signals available at connector J5 after the proper
set-up commands have been sent to it using the serial MT9M02_SCLK and MT9M02_SDATA signals, as discussed
in the Aptina MT9M024 data sheet. The HiSPi clock and data signals have the “SLVS” text in the signal name, they
are differential output signal pairs with “P” and “N” polarities, and they are biased at the +0.2V common mode level.
The receiving LatticeECP3™ device should be set to LVDS, 100 ohm differential termination. The other signals on
J5 are single-ended LVCMOS type and switch between the VDDIO level and GND. The J5 signal connections at
the Aptina MT9M024 devices, HiSPi connector J5, and LatticeECP3 on the Lattice HDR-60 Base Board are shown
in Table 2.
Table 2. Sensor (U1) Interface to HiSPi Connector J5
NanoVesta Head Board
J5 Pin
MT9M024 I/O Pin
HDR-60 Base Board
Polarity
LatticeECP3
I/O Pin
1
P
K21
2
N
L21
2
Signal
sysIO™ Bank
13
A3
MT9M02_SLVS0P
11
A2
MT9M02_SLVS0N1
29
A5
MT9M02_SLVS1P1
P
L22
2
27
A4
MT9M02_SLVS1N1
N
M22
2
21
B5
MT9M02_SLVS2P
1
P
P21
2
19
B4
MT9M02_SLVS2N1
N
N22
2
26
C4
MT9M02_SLVS3P1
P
M18
2
24
C3
MT9M02_SLVS3N1
N
N17
2
18
B3
MT9M02_SLVSCP
1
P
M21
2
16
B2
MT9M02_SLVSCN1
N
M20
2
4
—
VDDIO_rH
—
A13
1
10
H8
MT9M02_RESET_BAR1
—
C13
1
12
—
MT9M02_LED1
—
L19
2
30
D3
MT9M02_SDATA1
—
J22
2
—
C14
1
32
D2
MT9M02_SCLK
1
1. Signals labeled MT9M02* can be used for the MT9M024 image sensor.
5
MT9M024 NanoVesta Head Board
User’s Guide
Parallel Connector (J4)
The Aptina MT9M024 (U1) can produce parallel LVCMOS video signals available at connector J4 after the proper
set-up commands have been sent to it using the serial MT9M02_SCLK and MT9M02_SDATA signals, as discussed
in the Aptina MT9M024 data sheet. The J4 signal connections at the Aptina MT9M024 device, parallel connector
J4, and LatticeECP3 on the HDR-60 Base Board are shown in Table 3.
Table 3. Sensor (U1) Interface to Parallel Connector J4
NanoVesta Head Board
J4 Pin
MT9M024 I/O Pin
HDR-60 Base Board
Signal
LatticeECP3 I/O Pin
sysIO Bank
1
16
H1
MT9M02_DOUT0
J20
2
20
H2
MT9M02_DOUT11
G22
2
15
H3
MT9M02_DOUT2
1
F22
2
19
H4
MT9M02_DOUT31
J18
2
14
G1
MT9M02_DOUT4
1
A16
1
18
G2
MT9M02_DOUT51
J19
2
1
13
G3
MT9M02_DOUT6
C16
1
17
G4
MT9M02_DOUT71
E22
2
22
F1
MT9M02_DOUT81
G21
2
24
F2
MT9M02_DOUT91
G14
1
1
21
F3
MT9M02_DOUT10
J17
2
23
F4
MT9M02_DOUT111
C17
1
10
E3
MT9M02_PIXCLK1
C12
1
9
C1
MT9M02_EXTCLK_FPGA1
A19
1
11
E1
MT9M02_LINE_VALID1
A18
1
12
E2
MT9M02_FRAME_VALID1
B16
1
1
25
G7
MT9M02_TRIGGER
B18
1
27
H8
MT9M02_RESET_BAR1
A17
1
1
29
G8
MT9M02_OUTPUT_EN_BAR
F16
1
31
A8
MT9M02_STANDBY1
F15
1
1
26
D1
MT9M02_SADDR
G15
1
28
D2
MT9M02_SCLK1
D15
1
30
D3
MT9M02_SDATA1
C15
1
32
—
MT9M02_OSZ_ENABLE1
E15
1
4
—
VDDIO_rP
A12
1
1. Signals labeled MT9M02* can be used for MT9M024 image sensors.
Test and I2C Expansion Connector (J1)
The Test and I2C Expansion Connector provides access to serial I2C signals that can be used to control the Aptina
MT9M024 (U1) by an external controller. There is also a MT9M02_FLASH output that is active when the sensor is
acquiring the video image, which can be useful to trigger a Flash lamp. The Test and I2C Expansion Connector signals are shown in Table 4.
6
MT9M024 NanoVesta Head Board
User’s Guide
Table 4. Sensor (U1) Interface to Test and I2C Expansion Connector (J1)
NanoVesta Head Board
HDR-60 Base Board
J1 Pin
MT9M024 I/O Pin
Signal
LatticeECP3 I/O Pin
sysIO Bank
1
—
2
—
+5V
—
—
+5V
—
—
3
—
VDDIO
4
D1
MT9M02_SADDR1
5
—
GND
6
D2
MT9M02_SCLK1
1
A12, A13
1
G15
1
—
—
D15
1
7
D3
MT9M02_SDATA
C15
1
8
E4
MT9M02_FLASH1
—
—
1. Signals labeled MT9M02* can be used for MT9M024 image sensors.
Changes Made to Board in Revision 2
Revision 2 of the NanoVesta board was built to dissipate more heat from image sensor IC. The ground and power
planes were modified to 1-ounce copper and the mounting holes were connected to the ground plane. Many components were moved to different locations on the PCB, but maintain the same functionality as the Revision A board.
References
• HDR-60 Video Camera Development Kit web page
• DS1021, LatticeECP3 Family Data Sheet
• HB1009, LatticeECP3 Family Handbook
• EB59, HDR-60 Base Board User’s Guide
• QS010, LatticeECP3 Video Camera Development Kit QuickSTART Guide
Ordering Information
The 9MT024 Sensor NanoVesta Head Board is designed solely for use with the HDR-60 Video Camera Development Kit. One 9MT024 Sensor NanoVesta Head Board is included with the HDR-60 Video Camera Development
Kit, or it is available separately as a stand-alone item.
Description
9MT024 Sensor NanoVesta Head Board
Ordering Part Number
LF-9MT024NV-EVN
HDR-60 Video Camera Development Kit
(Contains: HDR-60 Base Board with LatticeECP3
FPGA pre-loaded with Image Signal Processing (ISP)
Demo, NanoVesta Head Board with Aptina A-1000
LFE3-70EAHDR60-DKN
720p HDR Sensor and Sunex lens, two USB cables,
HDMI cable with HDMI-to-DVI adapter, 12V AC
adapter power supply, QuickSTART Guide)
7
China RoHS Environment Friendly
MT9M024 NanoVesta Head Board
User’s Guide
Technical Support Assistance
Hotline: 1-800-LATTICE (North America)
+1-503-268-8001 (Outside North America)
e-mail: [email protected]
Internet: www.latticesemi.com
Revision History
Date
Version
February 2011
01.0
Initial release.
Change Summary
May 2012
01.1
Updated document with new corporate logo.
Document title changed from “NanoVesta Head Board User’s Guide” to
“MT9024 NanoVesta Head Board User’s Guide”.
Updated document to support NanoVesta Head Board Revision 2.
© 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as
listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of
their respective holders. The specifications and information herein are subject to change without notice.
8
9
A
B
C
D
MT9M02_SLVS1P
MT9M02_SLVS1N
MT9M02_SLVS2P
MT9M02_SLVS2N
MT9M02_SLVS3P
MT9M02_SLVS3N
MT9M02_SLVSCP
MT9M02_SLVSCN
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
VDD+0.4V
B3
B2
C4
C3
B5
B4
A5
A4
A3
A2
C2
SLVSCP
SLVSCN
SLVS3P
SLVS3N
SLVS2P
SLVS2N
SLVS1P
SLVS1N
SLVS0P
SLVS0N
VDD_SLVS
MT9M021/M023_HISPI
U1A
MT9M023IA3XTC
High-Speed Serial Pixel Interface
+5V0
5
GND
0.01uF
100nF/X7R
EN
LDO
EN
LDO
EN
LDO
EN
LDO
1ms RC
1ms RC
1ms RC
GND
C2
C18
VDD+0.4V
GND
1nF
C1
4
VDD+0.4V, +0.4V, 300 mA
VCC+1.8V, +1.8V, 300 mA
VDD_IO, +1.8V/+2.8V, 300 mA
VAA+2.8V, +2.8V, 300 mA
Power Supply Block Diagram
High speed signals use matched length 50 ohm traces
MT9M02_SLVS0P
MT9M02_SLVS0N
[5]
[5]
HISPI Interface
4
3
3
GND
1ms RC
GND
100K-0402SMT
R22
MP3
B&F Fastener Supply, MHNZ 002
6
3
0.01uF
C13
10uF/6V3/X7R
C15
MP1
B&F Fastener Supply, MPMS 002 0008 PH
SCREW & NUT
VCC+1.8V
GND
100nF
C11
1R
R31
+5V0
2
LENS
EN
IN
U2
LTC3025
2
1
BIAS
GND
PWP
ADJ
OUT
5
4
GND
LTC3025EDC#PBF
Sunex DSL946C
LN1
LH1
Sunex CMT821
Date:
Size
B
Title
LENS HOLDER
GND
2
7
5
GND
SCREW & NUT
Thursday, August 26, 2010
1
Sheet
2
of
7
2
Rev
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
MP4
B&F Fastener Supply, MHNZ 002
MP2
B&F Fastener Supply, MPMS 002 0008 PH
NANOVESTA-MT9M023_Sensor board
Project
402R
R13
Vout = 0.4*(1+R17/R18) = 0.4v
GND
10uF/6V3/X7R
VDD+0.4V
HISPI Interface
R18
40_2K
R0402
R17
0R
R0402
C10
VDD+0.4V
0.4v
300mA
1
A
B
C
D
MT9M024 NanoVesta Head Board
User’s Guide
Appendix A. Schematic
Figure 3. HiSPi Interface
A
B
C
D
5
100nF
GND
10uF/6V3
100nF
VAA
GND
10uF/6V3
U1B
GND
100nF
C21
10uF/6V3
C6
GND
4
VAA_PIX
GND
100nF
C20
GND
GND
100nF
C24
100nF
C25
H5
G5
F5
E5
D5
D4
C5
C8
C7
GND
DGND_H5
DGND_G5
DGND_F5
DGND_E5
DGND_D5
DGND_D4
DGND_C5
AGND_C8
AGND_C7
MT9M023IA3XTC
VDD_IO_E6
VDD_IO_F6
VDD_IO_G6
VDD_IO_H6
VDD_IO_H7
VAA_PIX_D7
VAA_PIX_D8
VDD_PLL
VDD_A6
VDD_A7
VDD_B6
VDD_C6
VDD_D6
VAA_B7
VAA_B8
MT9M021/M023_POWER
VDD_IO
E6
F6
G6
H6
H7
C5
D7
D8
VAA_PIX
VDD_IO
C26
GND
100nF
C23
B1
A6
A7
B6
C6
D6
VDD
VDD_PLL
B7
B8
VAA
C3
GND
100nF
100nF
GND
C19
C22
FB1
1
2
Z-600 ohm / 74279265
FB5
1
2
Z-600 ohm / 74279265
FB3
1
2
Z-600 ohm / 74279265
FB4
1
2
Z-600 ohm / 74279265
FB2
1
2
Z-600 ohm / 74279265
C17
GND
GND
VDD_PLL
VDD
VDDIO
VAA+2.8V
VAA+2.8V
VCC+1.8V
VAA+2.8V
Power & Regulators
4
GND
GND
10uF/6V3
C7
10uF/6V3
C4
3
3
VDDIO
GND
C33
1R
GND
1ms RC
GND
6
3
0.01uF
C32
10uF/6V3/X7R
1R
100K-0402SMT
R47
C29
GND
R49
+5V0
6
3
6
3
0.01uF
C14
10uF/6V3/X7R
1ms RC
100nF
C31
GND
R23
C16
R32
100K-0402SMT
100nF
1R
+5V0
GND
10uF/6V3/X7R
C12
VAA+2.8V
GND
GND
100nF
C30
R48
+5V0
EN
IN
U5
LTC3025
EN
IN
U3
LTC3025
EN
IN
U4
LTC3025
1
BIAS
GND
PWP
GND
2
7
1
BIAS
GND
PWP
GND
2
7
1
BIAS
GND
PWP
10
GND
2
7
5
5
4
GND
5
4
ADJ
OUT
5
4
2
GND
R46
10_0K
R0402
GND
GND
R40
1_8K
Date:
Size
B
Title
Thursday, August 26, 2010
1
Sheet
3
of
7
NANOVESTA-MT9M023_Sensor board
Project
Power & Regulators
2
Rev
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
Vout = 0.4*(1+R44/R46) = 1.792v
10uF/6V3/X7R
C28
VCC+1.8V
1
Vout = 0.4*(1+R16/(R20+R19))
= 2.816v {J3 on}
= 1.822v {J3 off}
J3
HEADER 2
1_8K
1
2
R14
GND
VDDIO
C9
VCC+1.8V
1.8v
300mA
R44
34_8K
R0402
2_8K
10uF/6V3/X7R
6_98K
R0402 GND
R20
GND
10_0K
R0402
R16
60_4K
R0402
GND
R41
VAA+2.8V
Vout = 0.4*(1+R43/R45) = 2.816v
10uF/6V3/X7R
VDDIO
1.8v/2.8v
300mA
R45
10_0K
R0402
GND
C27
VAA+2.8V
2.8v
300mA
R43
60_4K
R0402
R19
LTC3025EDC#PBF
ADJ
OUT
LTC3025EDC#PBF
ADJ
OUT
LTC3025EDC#PBF
2
A
B
C
D
MT9M024 NanoVesta Head Board
User’s Guide
Figure 4. Power and Regulators
11
GND
100nF
C8
5
GND
VDDIO
MT9M02_STANDBY
MT9M02_TRIGGER
[5]
[5]
VDDIO
MT9M02_LINE_VALID
MT9M02_FRAME_VALID
[5]
[5]
2
R29
R9
OUT
ENABLE
3
1
[5]
R12
21R
21R
R0402
21R
GND
R0402
R0402
R0402
R0402
R15
4K7
R0402
VDDIO
R0402
MT9M02_EXTCLK_FPGA
DSC1001-CE-27.0000
GND
VDD
Y1
21R
21R
MT9M02_STANDBY
R3
R4
MT9M02_EXTCLK
4
21R
R0402
R0402
21R
R28
21R
R11
R30
MT9M02_SCLK
MT9M02_SADDR
MT9M02_SDATA
MT9M02_OUTPUT_EN_BAR
MT9M02_RESET_BAR
MT9M02_FLASH
MT9M02_SCLK
MT9M02_SADDR
MT9M02_SDATA
MT9M02_OUTPUT_EN_BAR
MT9M02_PIXCLK
[5]
[5]
[5]
[5]
[5]
MT9M02_RESET_BAR
[5]
MT9M02_EXTCLK
MT9M023IA3XTC
NC_E7
NC_E8
NC_F8
NC/FLASH
STANDBY
TEST
TRIGGER
LINE_VALID
FRAME_VALID
SCLK
SADDR
SDATA
PIXCLK
OUTPUT_EN_BAR
RESET_BAR
EXTCLK
1
2
3
J2
HEADER 3
MT9M02_EXTCLK_OSC
4
[5]
MT9M021/M023_BASE
U1C
MT9M02_OSZ_ENABLE
E7
E8
F8
E4
A8
F7
G7
E1
E2
D2
D1
D3
E3
G8
H8
C1
MT9M02_EXTCLK_FPGA
4
MT9M021/M023
MT9M02_EXTCLK
DOUT0
DOUT1
DOUT2
DOUT3
DOUT4
DOUT5
DOUT6
DOUT7
DOUT8
DOUT9
DOUT10
DOUT11
H1
H2
H3
H4
G1
G2
G3
G4
F1
F2
F3
F4
3
3
R5
R6
R7
R8
R2
R33
R34
R37
R1
R25
R26
R38
21R
21R
21R
21R
21R
21R
21R
21R
21R
21R
21R
21R
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
R0402
MT9M02_SCLK
MT9M02_SDATA
MT9M02_FLASH
2
VDDIO
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
[5]
MT9M02_SADDR
MT9M02_DOUT0
MT9M02_DOUT1
MT9M02_DOUT2
MT9M02_DOUT3
MT9M02_DOUT4
MT9M02_DOUT5
MT9M02_DOUT6
MT9M02_DOUT7
MT9M02_DOUT8
MT9M02_DOUT9
MT9M02_DOUT10
MT9M02_DOUT11
2
GND
+5V0
R42
4K7
R0402
R10
4K7
R0402
1
2
3
4
5
6
7
8
FITTING1
Date:
Size
B
FITTING2
FITTING1
R27
2K2
R0402
R21
1K5
R0402
Thursday, August 26, 2010
1
Sheet
4
of
7
NANOVESTA-MT9M023_Sensor board
Project
GND
R39
4K7
R0402
R24
1K5
R0402
VDDIO
1
2
Rev
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
GND
GND
Image Sensor
FITTING2
Title
PIN1
PIN2
PIN3
PIN4
PIN5
PIN6
PIN7
PIN8
J1
DNL (SH-BM08B-SRSS)
TEST & I2C Expansion
MT9M02_OUTPUT_EN_BAR
MT9M02_STANDBY
MT9M02_SADDR
MT9M02_SDATA
MT9M02_SCLK
MT9M02_RESET_BAR
JST SH Series
A
B
C
D
Image Sensor
5
A
B
C
D
MT9M024 NanoVesta Head Board
User’s Guide
Figure 5. Image Sensor
12
A
B
C
MT9M02_SLVS0N
MT9M02_SLVS0P
MT9M02_SLVS2N
MT9M02_SLVS2P
MT9M02_SLVS1N
MT9M02_SLVS1P
[2]
[2]
[2]
[2]
[2]
[2]
5
+5V0
GND
FITTING2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
FITTING1
FITTING2
PIN1
PIN3
PIN5
PIN7
PIN9
PIN11
PIN13
PIN15
PIN17
PIN19
PIN21
PIN23
PIN25
PIN27
PIN29
PIN31
PIN33
PIN35
PIN37
PIN39
FITTING1
BOSS2
PIN2
PIN4
PIN6
PIN8
PIN10
PIN12
PIN14
PIN16
PIN18
PIN20
PIN22
PIN24
PIN26
PIN28
PIN30
PIN32
PIN34
PIN36
PIN38
PIN40
BOSS1
GND
GND
R52
4_7K
R0402
+5V0
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BOSS1
4
[2]
[2]
[2]
[2]
MT9M02_SDATA [4]
MT9M02_SCLK [4]
MT9M02_SLVS3N
MT9M02_SLVS3P
MT9M02_SLVSCN
MT9M02_SLVSCP
MT9M02_RESET_BAR
MT9M02_LED
VDDIO_rH
R35
0R
R0402
VDDIO
3
GND
D2
HSMC-C540-F0001(LowCurrent/2mA)
R54
1_5K
R0402
VAA+2.8V
3
POWER STATUS LEDS
+5V0
D1
HSMC-C540-F0001(LowCurrent/2mA)
R53
1k
R0402
VCC+1.8V
Hirose DF12 Series
J5
DF12(4.0)-40DP-0.5V_HEADER
HISPI : 0.4v // Other 2.8v or 1.8v
MIXED I/O Voltage
HISPI Sensor interface connector
INTERFACE - CONNECTOR,Right side
4
GND
MT9M02_EXTCLK_FPGA
MT9M02_LINE_VALID
MT9M02_DOUT6
MT9M02_DOUT2
MT9M02_DOUT7
MT9M02_DOUT3
MT9M02_DOUT10
MT9M02_DOUT11
MT9M02_TRIGGER
MT9M02_RESET_BAR
MT9M02_OUTPUT_EN_BAR
MT9M02_STANDBY
D3
HSMC-C540-F0001(LowCurrent/2mA)
R50
4_7K
R0402
+5V0
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
1
GND
FITTING2
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
FITTING1
FITTING2
PIN1
PIN3
PIN5
PIN7
PIN9
PIN11
PIN13
PIN15
PIN17
PIN19
PIN21
PIN23
PIN25
PIN27
PIN29
PIN31
PIN33
PIN35
PIN37
PIN39
FITTING1
BOSS2
PIN2
PIN4
PIN6
PIN8
PIN10
PIN12
PIN14
PIN16
PIN18
PIN20
PIN22
PIN24
PIN26
PIN28
PIN30
PIN32
PIN34
PIN36
PIN38
PIN40
BOSS1
BOSS2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
BOSS1
J4
DF12_40DS-0.5V_RECEPTACLE
GND
+5V0
MT9M02_PIXCLK [4]
MT9M02_FRAME_VALID
MT9M02_DOUT4 [4]
MT9M02_DOUT0 [4]
MT9M02_DOUT5 [4]
MT9M02_DOUT1 [4]
MT9M02_DOUT8 [4]
MT9M02_DOUT9 [4]
MT9M02_SADDR [4]
MT9M02_SCLK [4]
MT9M02_SDATA [4]
MT9M02_OSZ_ENABLE
VDDIO_rP
[4]
[4]
R36
0R
R0402
VDDIO
2
MT9M02_LED
D4
HSMC-C540-F0001(LowCurrent/2mA)
R51
1_5K
R0402
VAA+2.8V
Date:
Size
B
Title
Thursday, August 26, 2010
1
Sheet
5
of
7
NANOVESTA-MT9M023_Sensor board
Project
Interface Connectors
2
Rev
Lattice Semiconductor Corporation
5555 N.E. Moore Court
Hillsboro, Oregon. 97124
Fitting & Boss have no electrical function, can be used as vias
+5V0
PARALLEL Sensor interface connector
INTERFACE - CONNECTOR,Left side
2
Hirose DF12 Series
D
5
A
B
C
D
MT9M024 NanoVesta Head Board
User’s Guide
Figure 6. Interface Connectors