Download Lecture 13: Combinational Circuit Design

Digital VLSI design
Lecture 13:
Combinational Circuit Design
HI- and LO-Skew
 Def: Logical effort of a skewed gate for a particular
transition is the ratio of the input capacitance of
that gate to the input capacitance of an unskewed
inverter delivering the same output current for the
same transition.
 Skewed gates reduce size of noncritical transistors
 HI-skew gates favor rising output (small nMOS)
 LO-skew gates favor falling output (small pMOS)
 Logical effort is smaller for favored direction
 But larger for the other direction
2
Catalog of Skewed Gates
Inverter
NAND2
2
unskewed
1
Y
guu = 1
gdd = 1
gavg
=1
avg
A
2
B
2
2
HI-skew
2
A
Y
1/2 gu
u
gdd
gavg
avg
= 5/6
= 5/3
= 5/4
B
1
A
1
1
Y
guu = 4/3
gdd = 2/3
gavg
=1
avg
1
A
2
B
2
3
4
A
4
1
guu = 4/3
gdd = 4/3
gavg
= 4/3
avg
Y
1
B
Y
2
A
1
LO-skew
2
Y
2
A
NOR2
1
B
4
A
4
guu = 5/3
gdd = 5/3
gavg
= 5/3
avg
Y
guu
gdd
gavg
avg
1/2
=1
=2
= 3/2
guu
gdd
gavg
avg
= 3/2
=3
= 9/4
2
B
A
Y
1/2
2
Y
guu = 2
gdd = 1
gavg
= 3/2
avg
1
1
guu = 2
gdd = 1
gavg
= 3/2
avg
Asymmetric Skew
 Combine asymmetric and skewed gates
 Downsize noncritical transistor on unimportant input
 Reduces parasitic delay for critical input
A
reset
Y
2
1
A
4/3
4
reset
4
Y
Best P/N Ratio
 We have selected P/N ratio for unit rise and fall
resistance (m = 2-3 for an inverter).
 Alternative: choose ratio for least average delay
 Ex: inverter






Delay driving identical inverter
A
tpdf = (P+1)
tpdr = (P+1)(m/P)
tpd = (P+1)(1+m/P)/2 = (P + 1 + m + m/P)/2
dtpd / dP = (1- m/P2)/2 = 0
Least delay for P =
m
5
P
1
P/N Ratios
 In general, best P/N ratio is sqrt of equal delay
ratio.
 Only improves average delay slightly for inverters
 But significantly decreases area and power
Inverter
NAND2
2
fastest
P/N ratio
A
1.414
Y
1
gu = 1.15
gd = 0.81
gavg = 0.98
NOR2
2
Y
A
2
B
2
6
B
2
A
2
Y
gu = 4/3
gd = 4/3
gavg = 4/3
1
1
gu = 2
gd = 1
gavg = 3/2
Observations
 For speed:
 NAND vs. NOR
 Many simple stages vs. fewer high fan-in stages
 Latest-arriving input
 For area and power:
 Many simple stages vs. fewer high fan-in stages
7
Another Example
8
Circuit Families
Outline
 Pseudo-nMOS Logic
 Dynamic Logic
 Pass Transistor Logic
10
Introduction
 What makes a circuit fast?




I = C dV/dt -> tpd  (C/I) DV
low capacitance
high current
small swing
 Logical effort is proportional to C/I
 pMOS are the enemy!
 High capacitance for a given current
B
4
A
4
Y
1
1
 Can we take the pMOS capacitance off the input?
 Various circuit families try to do this…
11
Pseudo-nMOS
 In the old days, nMOS processes had no pMOS
 Instead, use pull-up transistor that is always ON
 In CMOS, use a pMOS that is always ON
 Ratio issue
 Make pMOS about ¼ effective strength of pulldown
network
1.8
1.5
load
P/2
1.2
P = 24
Ids
Vout 0.9
Vout
0.6
P = 14
16/2
0.3
Vin
P=4
0
0
0.3
0.6
0.9
Vin
12
1.2
1.5
1.8
Pseudo-nMOS Gates
 Design for unit current on output
to compare with unit inverter.
 pMOS fights nMOS
Y
inputs
f
Inverter
Y
A
NAND2
gu
gd
gavg
pu
pd
pavg
=
=
=
=
=
=
A
B
NOR2
gu
g
Y gd
avg
pu
pd
pavg
13
=
=
=
=
=
=
A
B
gu
gd
gavg
Y pu
pd
pavg
=
=
=
=
=
=