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S. Mancini ASIC vs FPGA Problématique Plan Introduction ASICs FPGA Modèles de coûts FPGA ou ASIC ? Méthodologie de conception Durcissement aux radiations SoC Bilan Sur quels critères fonder son choix ? Quels sont les points communs et différences des méthodes de conception ? 2- ASIC vs FPGA Introduction 1- ASIC vs FPGA S. Mancini Les familles Plan Les ASICs (Application Specific Integrated Circuit) se décomposent en plusieurs familles : Full Custom Introduction ASICs FPGA Modèles de coûts Les masques des transistors sont dessinés. Standard cells Le circuit est un assemblage de cellules placées/routées. Méthodologie de conception Durcissement aux radiations SoC Bilan Gate array Une “mer” de portes est routée. Embedded Gate array C’est un Gate array avec des macro-blocs complexes (RAM). 3- ASIC vs FPGA 4- ASIC vs FPGA Introduction- ASICs Process Generation Technology Trends Evolution des technologie 250nm 250nm • • 130nm 100nm 90nm • ASICs FPGA Modèles de coûts ′00 ITRS ′01 ITRS • ♦ Leading Foundry ♦ 65nm 1997 1997 1999 1999 2001 2001 UK Design Forum Technologie 90 nm 5- ASIC vs FPGA Introduction- ASICs Introduction ′99 ITRS (International Technology Roadmap for Semiconductors) • 180nm 180nm 1st April, 2003 Plan 2003 2003 Year 2005 2005 2007 2007 2009 2009 1 430 KPortes/mm2 SRAM 1.6 à 1.2 mm2 par Mbit DRAM 0.5 mm2 par Mbit 6 à 9 couches de métal 6 Méthodologie de conception Durcissement aux radiations SoC Bilan 6- ASIC vs FPGA S. Mancini S. Mancini Principe Technologies de programmation Proposer des circuits génériques reconfigurables à volonté. Ils sont constitués de matrices de cellules reconfigurables et d’un réseau d’interconnexion. Les trois principales technologies de programmation sont : Q SRAM Principaux vendeurs : Actel Altera Atmel Cypress Q’ RW Data Lattice Minc QuickLogic Xilinx Flash Les technologies diffèrent par : Anti-fusibles La technologie de mémorisation de la configuration Le type de cellules élémentaires 7- ASIC vs FPGA Introduction- FPGA S. Mancini Reconfigurable dynamiquement Technologie standard Perte de configuration à la mise hors tension 8- ASIC vs FPGA Introduction- FPGA S. Mancini Technologies de programmation Technologies de programmation Les trois principales technologies de programmation sont : Les trois principales technologies de programmation sont : Grille flottante SRAM Conserve la configuration Flash Anti−fusible SRAM Flash Circuit “autonome” Encombrement minimal Technologie non-standard Anti-fusibles Non reprogrammable Anti-fusibles Technologie spécifique Pr o A SI C P L U S F la s h F a m il y F P GA s Pr oA S I C PL U S A r c hi t e c t u r e PLUS The proprietary ProASIC architecture granularity comparable to gate arrays. the “Embedded Memory Configurations” section on page 21 for more information. provides Fla sh S wit ch The ProASICPLUS device core consists of a Sea-of-Tiles™ (Figure 1). Each tile can be configured as a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.) by 9- ASIC vs programming the FPGA appropriate Flash switch interconnections (Figure FPGA 2 on page 6 and Figure 3 on Introductionpage 6). Tiles and larger functions are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Flash switches are programmed to connect signal lines to the appropriate logic cell inputs and outputs. Dedicated high-performance lines are connected as needed for fast, low-skew global signal distribution throughout the core. Maximum core utilization is possible for virtually any design. Unlike SRAM FPGAs, ProASICPLUS uses a live on power-up ISP Flash switch as its programming element. In the ProASICPLUS Flash switch, two transistors share the floating gate, which stores the programming information. One is the sensing transistor, which is only used for writing and verification of the floating gate voltage. The other is the switching transistor. It can be used in the architecture to connect/separate routing nets or to configure logic. It is also used to erase the floating gate (Figure 2 on page 6). S. Mancini Pr o A S I C P L U S F la s h F a m il y F P GA s Floating Gate Logi c Ti le Sensing The logic tile cell (Figure 3 on page 6) has three inputs (any or all of which can be inverted) and one output (which can connect to both ultra-fast local and efficient long-line routing resources). Any three-input, one-output logic function (except a three-input XOR) can be configured as one tile. The tile can be configured as a latch withFigure clear 2or• Flash Switch set or as a flip-flop with clear or set. Thus, the tiles can flexibly map logic and sequential gates of a design. Actel (ProAsic) ProASICPLUS devices also contain embedded two-port SRAM blocks with built-in FIFO/RAM control logic. Programming options include synchronous or asynchronous operation, two-port RAM configurations, user defined depth and width, and parity generation or checking. Please see 10- ASIC vs FPGA Introduction- FPGA S. Mancini Switch In Switching Actel (Axcelerator) Word A x c e le r a t o r F a m il y F P GA s Switch Out SuperCluster C C TX TX RX RX TX TX RX RX A x c e le r a t o r F a m il y F P G C R B C R Local Routing In 1 Efficient Long-Line Routing 4k RAM/ FIFO RAM Block In 2 (CLK) 256x9 Two-Port SRAM or FIFO Block 4k RAM/ FIFO In 3 (Reset) Switch in Figure 3 • Core Logic Tile I/Os Rou ti ng Res our ces Logic Tile RAM Block 1 Grille flottante PLUS The routing structure of ProASIC devices is designed to provide high performance through a flexible four-level hierarchy of routing resources: ultra-fast local resources, Test efficient long-line resources, high speed very long-line resources, and high performance global networks. The ultra-fast local resources are dedicated lines that allow the output of each tile to connect directly to every input of the eight Mot surrounding tiles (Figure 4 on page 7). 256x9 Two Port SRAM The efficient long-line resources provide routing for longer or FIFO Block Figure 1 • The ProASICPLUS Device Architecture distances and higher fanout connections. These resources vary in length (spanning 1, 2, or 4 tiles), run both vertically and horizontally, and cover the entire ProASICPLUS device (Figure 5 on page 7). Each tile can drive signals onto the efficient long-line resources, which can in turn, access every input of every tile. Active buffers are inserted automatically by routing software to limit the loading effects due to distance and fanout. 1 The high-performance global networks are low skew, high Switch fanout nets that are accessible from external pins or from internal logic (Figure 7 on page 9). These nets are typically used to distribute clocks, resets, and other high fanout nets requiring a minimum skew. The global networks are implemented as clock trees, and signals can be introduced at any junction. These can be employed hierarchically with signals accessing every input on all tiles. 11- ASIC vs FPGA Introduction- FPGA 6 5 PLL Clocks SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC SC SC SC SC SC SC HD HD HD HD HD HD HD HD HD HD HD HD HD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RD RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC SC SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC RAMC SC SC SC SC SC SC RD SC SC SC Core TileSC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC RAMC SC SC SC SC SC SC RD SC SC SC SC SC SC I/O Structure (See Figure 6) Figure 2 • Axcelerator Family Interconnect Elements Actel’s Axcelerator family provides two types of logic modules, the register cell (R-cell) and the combinatorial Figure 6 • AX Device Architecture (AX1000 shown) 1 cell (C-cell). The AX C-cell can implement more than 4,000 In addition, every SRAM block has an embedded FIFO Table 1 • Number of Core Tiles per Device combinatorial functions of up to 5 inputs (Figure 3 on control unit. The control unit allows the SRAM block to be Device Number of Core Tiles page 5). The C-cell contains carry logic for even more configured as a synchronous FIFO without using core logic efficient implementation of arithmetic functions. With its AX125 1 regular tile modules. The FIFO width and depth are programmable. The small size, the C-cell structure is extremely AX250 4 smaller tiles FIFO also features programmable ALMOST-EMPTY synthesis-friendly, simplifying the overall design as well as AX500 4 regular tiles (AEMPTY) and ALMOST-FULL (AFULL) flags in addition to reducing design time. AX1000 9 regular tiles the normal EMPTY and FULL flags. The embedded FIFO AX2000 16 regular tiles The R-cell contains control unit also contains the counters necessary for thea flip-flop featuring asynchronous clear, preset, generation of the read and write addressasynchronous pointers as well as and active-low enable control signals (Figure on page 5). The R-cell registers feature Embedded Memory control circuitry to prevent metastability and3 erroneous programmable clock polarity selectable on a operation. The embedded SRAM/FIFO blocks can be As mentioned earlier, each core tile has either three (in a cascaded to create larger configurations.register-by-register basis. This provides additional flexibility smaller tile) or four (in the regular tile) embedded SRAM (e.g., easy mapping of dual-data-rate functions into the blocks along the west side, and each variable-aspect-ratio FPGA) while conserving valuable clock resources. The clock SRAM block is 4,608 bits in size. Available memory source for the R-cell can be chosen from the hard-wired configurations are: 128x36, 256x18, 512x9, 1kx4, 2kx2 or 12- ASIC vs FPGA clocks, the routed clocks, or the internal logic. 4kx1 bits. The individual blocks have separate read and IntroductionTwo C-cells, a single R-cell, and two Transmit (TX) and two write ports thatFPGA can be configured with different bit widths Receive (RX) routing buffers form a Cluster, and two on each port. For example, data can be written in by 8 and Clusters comprise a SuperCluster (Figure 4 on page 5). read out by 1. The embedded SRAM blocks can be initialized Each SuperCluster contains an independent Buffer module, at power up via the device JTAG port (ROM emulation which supports automatic buffer insertion on high-fanout mode). nets by the place-and-route tool, minimizing system delays while improving logic utilization. Circuit AX2000 2 88 1 Logic Modules Circuit APA100 1 000 000 56 320 198 kBit 4k RAM/ FIFO SC RAMC Switch out Flash System Gates v3.1 Tiles (Registers) RAM Chip Layout The high-speed very long-line resources, which span the entire device with minimal delay, are used to route very long or very high fanout nets. (Figure 6 on page 8). 4k RAM/ FIFO RAMC System Gates R-Cells C-Cells v3.1 S. Mancini 6 2 000 000 10 752 21 504 RAM PLL Clocks 338 kBit 8 4 The logic modules within the SuperCluster are arrange that two combinatorial modules are side by side, givin C–C–R – C–C–R pattern to the SuperCluster. This C–C pattern enables efficient implementation (minimum de of 2-bit carry logic for improved arithmetic performa (Figure 5 on page 5). The AX architecture is fully fracturable, meaning that if or more of the logic modules in a SuperCluster are used particular signal path, the other logic modules are available for use by other paths. At the chip level, SuperClusters are organized into c tiles, which are arrayed to build up the full chip. Each c tile consists of an array of 336 SuperClusters and four SR blocks (176 SuperClusters and 3 SRAM blocks for AX250). The SRAM blocks are arranged in a column on west side of the tile (Figure 6 on page 6). For example, AX1000 is composed of a 3x3 array of 9 core t Surrounding the array of core tiles are blocks of I/O Clus and the I/O bank ring (Table 1 on page 6). S. Mancini Advanced v1.5 4 Advanced v1.5 tent of ured as alue in write Columns Blocks in Kb in Bits XC2VP2 Device 4 12 216 221,184 XC2VP4 4 28 504 516,096 XC2VP7 6 44 792 811,008 XC2VP20 8 88 1,584 1,622,016 XC2VP30 8 136 2,448 2,506,752 XC2VP40 10 192 3,456 3,538,944 XC2VP50 12 232 4,176 4,276,224 XC2VP70 14 328 5,904 6,045,696 XC2VP100 16 444 7,992 8,183,808 XC2VP125 18 556 10,008 R Functional Description: FPGA Configurable Logic Blocks (CLBs) 10,248,192 The Virtex-II Pro configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a switch matrix to access the general routing matrix, as shown in Figure 23. Xilinx (Spartan 3/Virtex II) ge) Figure 43 shows the layout of the block RAM columns in the XC2VP4 device. 2_050901 DCM COUT RocketIO TM Functional Description: FPGA Serial Transceivers DCM TBUF TBUF Configurable Logic Blocks (CLBs) endent All conion. A CLB element comprises 4 similar slices, with fast local Slice feedback within the CLB. The four slices are split in two colX1Y0 umns of two slices with two independent carry logic chains COUT Switch and one common shift chain. The Virtex-II Pro configurable logic blocks (CLB) are organized in an array and are used to build combinatorial and synchronous logic designs. Each CLB element is tied to a CLBs switch matrix to access the general routing matrix, as shown in Figure 23. CLBs BRAM Multiplier Blocks Matrix Slice Description Slice CLBs CLBs Each slice includes two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and two storage elements. As shown in Figure 24, each 4-input function generator is programmable as a 4-input LUT, 16 bits of distributed SelectRAM+ memory, or a 16-bit variable-tap shift register element. COUT Matrix Slice X1Y0 CIN MUXFx SRL16 LUT G SRL16 ORCY LUT F MUXFx SRL16 Fast Connects to neighbors LUT G CY Figure 24: Virtex-II Pro Slice Configuration MUXF5 Figure 23: Virtex-II Pro CLB Element SRL16 LUT F CY Register/ Latch Arithmetic Logic DCM RocketIO TM Serial Transceivers DCM Figure 24: Virtex-II Pro Slice Configuration 1 Circuit Mult. (18x18) Clock man. µP 18-Bit x 18-Bit Multipliers Logic Cells 74 880 125 136 Slices 33080 55 616 A Virtex-II Pro multiplier block is an 18-bit by 18-bit 2’s comRAM signed multiplier. 2,5 MBit MBit plement Virtex-II Pro 11 devices incorporate Introduction many embedded multiplier blocks. These multipliers can be associated with an 18 Kb block SelectRAM+ resource or can be used independently. They are optimized for 13ASIC vs FPGA high-speed operations and have a lower power consumpIntroductionFPGA tion compared to an 18-bit x 18-bit multiplier in slices. 24 www.xilinx.com 1-800-255-7778 Circuit LEs RAM Mult. (9x9) PLL µP DS083-2_31_122001 DS083-2_11_010802 Figure 43: XC2VP4 Block RAM Column Layout 1 Circuit Spartan 3 VirtexII he total r each ks are ual-port Register/ Latch DS083-2_31_122001 RAM16 DS083-2_32_122001 ized in column Blocks, CY Arithmetic Logic Register/ Latch CIN NIT_xx egister serted ailable config- Register/ Latch MUXF5 CIN Slice X0Y0 CY RAM16 Figure 23: Virtex-II Pro CLB Element 1 RAM16 SHIFT Slice X0Y1 ute) ORCY RAM16 SHIFT DS083-2_32_122001 PPC405 CPU Switch CLBs Reset Slice X1Y1 Altera (Apex/Stratix) Slice Description Each slice includes X0Y1 two 4-input function generators, carry logic, arithmetic logic gates, wide function multiplexers and Slice two storage elements. As shown in Figure 24, each Fast 4-input function generator isX0Y0 programmable as a 4-input LUT, 16 Connects neighbors bits of distributed SelectRAM+ memory, or a to 16-bit variable-tap shift register element. CIN COUT TBUF TBUF R Slice X1Y1 A CLB element comprises 4 similar slices, with fast local feedback within the CLB. The four slices are split in two columns of two slices with two independent carry logic chains and one common shift chain. Spartan 3 104 4 0 VirtexII 556 12 4 PPC S. Mancini www.xilinx.com 1-800-255-7778 Apex II (EP2A70) 67 200 1 Mbit 4 Stratix (EP1S80) 79 040 7 Mbit 176 12 Excalibur (EPXA10) 38 400 3 Mbit ? ARM922T 14- ASIC vs FPGA Introduction- FPGA S. Mancini DS083-2 (v2.7) June 2, 2003 Advance Product Specification DS083-2 (v2.7) June 2, 2003 Advance Product Specification 24 www.xilinx.com 1-800-255-7778 DS083-2 (v2.7) June 2, 2003 Advance Product Specification Coûts des FPGAs Plan Exemple de prix unitaires pour de grandes quantités : Introduction ASICs FPGA Modèles de coûts Méthodologie de conception Durcissement aux radiations SoC Bilan 15- ASIC vs FPGA S’ajoute Société Altera Référence EP20K200 (Apex 20k) Prix 340 $ Altera Altera EP1S80 EPXA1 (Excalibur ARM) 800 $ 27 $ Xilinx XC3S1000 (Spartan 3) 200 $ Xilinx XC2V8000 (Virtex II) 8000 $ Xilinx XC2VP100 (Virtex II Pro) 11000 $ Actel APA1000 (ProAsic+) 400 $ Actel AX2000 (Axcelerator) 630 $ 16- ASIC vs FPGA Introduction- Modèles de coûts Outils de CAO EEPROMs externes S. Mancini Coût des ASICS Troix composantes : Coût de conception Ingénieurs Outils de CAO ≈ 500 000 $ par an. NRE (Non-Recurring Engineering Charges) Coûts de fabrication incompressibles (masques, . . . ) ≈ 50 000 $, jusqu’à 1,5 M$ pour wafer 300 mm techno 90 nm Coût unitaire Coût de fabrication unitaire ≈ 0.2 $ par mm2 Un wafer 300 mm (90000 mm2)= 300 $ Les gate-arrays réduisent les NRE. 18 17- ASIC vs FPGA Introduction- Modèles de coûts S. Mancini Total Unit Cost ( $400,000 FPGA Cost ASIC Cost $300,000 $200,000 $100,000 $5 10 50 100 150 # of Units Device + EDA Tools Estimate (ASIC includes NRE) FPGA EDA $ 82,000 Simulation+Synthesis+FPGA Place&Route ASIC EDAEach $ 343,000 Simulation+Synthesis+Timing+ATPG FPGA $ 3,200 Device Only Cost (ASIC includes NRE) Unit’s FPGA Cost ASIC Cost 5 $ 16,000 $ 350,150 ASIC includes NRE) 10 $ 32,000 $ 350,300 Cost ASIC Cost 50 $ 160,000 $ 351,500 320,000 $ 353,000 16,000 100 $ $ 350,150 480,000 $ 354,500 32,000 150 $ $ 350,300 - Comparaison ASIC Cost $ 693,300 $ 694,500 $ 696,000 $ 697,500 $ 699,000 $ 700,500 FPGA $ 351,500 353,000 354,500 NRE ($) Coût unitaire ($) 350 000 3 200 30 FPGA/ASIC Cost vs Units (250KGates) FPGA ASIC Total Unit Cost (US$) $600,000 $500,000 $400,000 FPGA/ASIC Cost vs Units (250KGates) Total Unit Cost (US$) $600,000 $500,000 $300,000 $1,000,000 $100,000 1 $5 $400,000 10 50 100 150 $800,000 $600,000 FPGA Cost $400,000 ASIC Cost # of Units $300,000 $200,000 $100,000 FPGA Cost $ 114,000 $ 242,000 $ 402,000 $ 562,000 $ 722,000 $ 882,000 # of Units ASIC Cost $ 693,300 $ 694,500 $ 696,000 $ 697,500 $ 699,000 $ 700,500 FPGA Cost ASIC Cost $200,000 $- Device + EDA Tools Estimate (ASIC includes NRE) $FPGA EDA $ 82,000 Simulation+Synthesis+FPGA Place&Route 50 100 150 ASIC EDA $ 5 343,000 10 Simulation+Synthesis+Timing+ATPG Unit’s 10 50 100 150 200 250 Plusieurs projets/circuits sont faits sur le même wafer pour partager les NRE. 30 Each 350,000 FPGA/ASIC Cost vs Units (250KGates) FPGA Cost ASIC Cost $200,000 - ASIC $ ASIC NRE $ Les circuits multi-projets 3,200 Each FPGA NRE $ Données : système de 250K portes $ $ $ Total Unit Cost (US$) 60,000 20,000 80,000 FPGA NRE $ ASIC $ Each Unit’s FPGA30Each Cost FPGA ASIC$NRE $3,200 350,000 114,000 FPGA NRE 10 $ $ ASIC 50 $ $ 30 242,000 Each $ 402,000 ASIC NRE100 $ 350,000 150 $ 562,000 200 $ 722,000 250 $ 882,000 10 50 100 150 200 250 # of Units FPGA $ 3,200 Each FPGA NRE $ - ASIC $ ASIC NRE $ Coût 1du circuit Europractice : AMI Semiconductor 0,35 µm CMOS 680 Euro/mm2 CMP : STMicroelectronics 0,18 µm CMOS HCMOS8D 990 Euro/mm2 30 Each . . . et1 la CAO 350,000 http ://www.altera.com/products/devices/cost/cst-cost_step1.jsp s Estimate (ASIC includes NRE) DA $ 82,000 Simulation+Synthesis+FPGA Place&Route FPGA/ASIC Cost vs Units (250KGates) DA $ 343,000 Simulation+Synthesis+Timing+ATPG $1,000,000 ASIC Cost 18- ASIC vs FPGA $800,000 $ 693,300 Introduction- Modèles de coûts $ 694,500 $600,000 $ 696,000 $400,000 $ 697,500 $200,000 $ 699,000 $ 700,500 $- FPGA $ Total Unit Cost (US$) 10 FPGA NRE $ ASIC $ ASIC NRE $ 50 100 150 3,200 Each 30 Each 350,000 200 FPGA Cost ASIC Cost S. Mancini 19- ASIC vs FPGA Méthodologie de conception S. Mancini 250 # of Units Plan Flot de conception FPGA/ASIC Cost vs Units (250KGates) $1,000,000 Total Unit Cost (US$) Cost 14,000 42,000 02,000 62,000 22,000 82,000 $800,000 Introduction Méthodologie de conception $600,000 FPGA Cost ASIC Cost $400,000 Spécification $200,000 $- 50 100 150 200 250 Méthodes communes # of Units Spécificité des ASICs Spécificité des FPGAs Le prototypage : FPGA vers ASIC Exemple de projet “multi-plateforme” : LEON 10 Vecteurs de test non VHDL (RTL) Synthèse Placement routage Simulation Simulation Simulation Validation oui Validation oui Validation Fabrication ASIC Durcissement aux radiations SoC Bilan 20- ASIC vs FPGA 21- ASIC vs FPGA Méthodologie de conception- Méthodes communes S. Mancini Synthèse directe Plan Introduction Méthodologie de conception Méthodes communes Spécificité des ASICs Spécificité des FPGAs Le prototypage : FPGA vers ASIC Exemple de projet “multi-plateforme” : LEON Durcissement aux radiations SoC Bilan 22- ASIC vs FPGA Programmation FPGA Les descriptions à un "haut" niveau d’abstraction des blocs fonctionnels sont transformées en cellules standards. VHDL Entity NETLIST Synthèse e 1 s e2 e3 Placement Routage LAYOUT Pas de circuits spécifiques de type RAM/CAM, PLL 23- ASIC vs FPGA Méthodologie de conception- Spécificité des ASICs S. Mancini Composants "précaractérisés"-IP Le “Back-End” Les circuits complexes sont proposés sous la forme de macro-blocs. VHDL NETLIST e1 e2 Entity Placement Insertion test Insertion arbre d’horloge Routage des horloges s e3 Les fondeurs proposent des modèles de simulation et des masques (vue abstraite). La synthèse se fait par instanciation de “boîte noire”. Le placement/routage se décompose en plusieurs étapes : RAM Routage complet Analyse de timing Vérification (DRC, LVS, simulation post placement/routage, ...) Application-Specific SOC Multiprocessors Les blocs fonctionnels peuvent être décomposés et placés/routés séparement LAYOUT MBS + VIP1 + VIP2 MPEG CAB chronously connected to the same clock in another chiplet, we phase-aligned these clocks and analyzed the signal paths to meet timing constraints. We achieved clock alignment by tweaking the clock insertion delays, using aligners in the clock module. Similarly, we made the clock trees as structurally identical as possible. As part of the physical design process, we met design completion and manufacturability goals by implementing techniques such as design rule checks, antenna fixes, track filling, and doubling of vias wherever possible. Figure 4 shows the layout plot for the Viper design’s initial version. Table 3 summarizes the major design parameters. ICP1 + ICP2 + MMI 1394 Conditional access (MSP1 + MSP2) T-PI MSP3 M-PI TM32 PR3940 WE HAVE LEARNED much from the Viper design experience and trust it will guide us in the future, particularly since the next-generation SOC designs are significantly more complex, calling for still higher levels of integration. Some of our current activities, in addition to regular chip-development tasks, are investigating more efficient on-chip bus architectures and better design-reuse methodologies. ■ Figure 4. Layout of Viper (PNX8500). PNX8500 (philips) 1 Table 3. Design statistics. IP Parameter Value Process technology TSMC 0.18 µm, six metal layers La physique des interconnexions doit être prise en compte. Transistors About 35 million 1.2 million instances, or 8 million gates Acknowledgments Memories 243 instances, 750-Kbit memory CPUs 2 (TriMedia TM32 and MIPS PR3940) We thank the Viper management and design teams for their hard work, particularly chief architects Gert Slavenburg and Lane Albanese, without whose foresight and leadership the project never would have been successful. Instances Peripherals 50 Clock domains 82 Clock speed TM32: 200 MHz; PR3940: 150 MHz; Power 4.5 W Supply voltage 1.8-V core and 3.3-V I/O Package BGA456 SDRAM: 143 MHz 24- ASIC vs FPGA Méthodologie de conception- Spécificité des ASICs S. Mancini References 1. S. Rathnam and G. Slavenburg, “An Architectural Overview of the Programmable Multimedia Processor, TM-1,’’ Proc. 41st IEEE Computer 25- ASIC vs FPGA Méthodologie de conception- Spécificité des ASICs Society Int’l Conf. (COMPCON 96), IEEE CS chiplet timing, clock matching, and I/O timing analysis. Press, Los Alamitos, Calif., 1996, pp. 319-326. S. Mancini 2. D. Paret and C. Fenger, The I2C Bus, John Wiley & Sons, New York, 1997. To achieve timing closure, we made engineering change orders to the netlist after routing. Following each manipulation step, formal verification ensured that the modified netlist was functionally equivalent to the one after test insertion. We aligned all clock domains having synchronous chiplet crossings. For example, if the memory interface clock in one chiplet was syn- 30 Santanu Dutta is a design engineering manager at Philips Semiconductors in Sunnyvale, California. His research interests include design of high-performance IEEE Design & Test of Computers Modèles d’entrées Plan Les vendeurs de FPGA proposent des outils “propriétaires” pour utiliser les FPGAs : Introduction Méthodologie de conception Saisie de schématique Langages de description spécifiques Méthodes communes Spécificité des ASICs Spécificité des FPGAs Le prototypage : FPGA vers ASIC Exemple de projet “multi-plateforme” : LEON AHDL - Altera ABEL - Xilinx La synthèse peut être réalisée par des outils tiers (Leonardo, Synplicity, Synopsys, etc ...). Durcissement aux radiations SoC Bilan 26- ASIC vs FPGA 27- ASIC vs FPGA Méthodologie de conception- Spécificité des FPGAs Placement/routage S. Mancini Utilisation des ressources Le placement/routage est réalisé par des outils propriétaires. Ces outils permettent : ? Comment utiliser les ressources des FPGAs ? Instanciation directe Primitives (macro-cells, RAM, etc ...) Bibliothèques de macrofonctions d’allouer les blocs fonctionnels d’extraire une analyse de timing Enveloppe Main Macro Synthèse Selon les outils de synthèse ces instances ne peuvent pas être synthétisées de façon classique L’acroissement de complexité des FPGA impose l’utilisation de méthodologies hiérarchiques. Enveloppe Placement Routage Description de haut niveau/ inférence Les synthétiseurs détectent les blocs complexes. Exemple : RAM, multiplieurs, etc ... 28- ASIC vs FPGA Méthodologie de conception- Spécificité des FPGAs S. Mancini 29- ASIC vs FPGA Méthodologie de conception- Spécificité des FPGAs S. Mancini Principe Plan On utilise des FPGAs pour valider la conception d’un ASIC. Introduction Méthodologie de conception Il existe des plateformes d’émulation génériques de Méthodes communes grandes complexité (Aptix, Quickturn, . . . ). Spécificité des ASICs Spécificité des FPGAs Accroissement de la vitesse de simulation Le prototypage : FPGA vers ASIC Exemple de projet “multi-plateforme” : LEON Solutions for Wireless Communications and Image Processing Pas de vérification temporelle Durcissement aux radiations SoC Bilan L’architecture de l’émulateur peut être inadaptée au projet User-controlled power supply voltage selection and monitoring to support advanced prototyping components today and tomorrow I/O cable connectors (20) with interleaved grounds provide flexible connection to target systems 31- ASIC vs FPGA Méthodologie de conception- Le prototypage : FPGA vers ASIC FPCB® user “freehole” area with 1,920 routable pins a wide variety 30- ASICaccommodates vs FPGA of prototyping components S. Mancini Modular low-skew clock circuits (8) Modular hard-wired buses for high-fanout bi-directional nets FPIC® Programmable Interconnect Components (3) provides software-controlled interconnect and diagnostic probing Exemple : Aptix Plan utions for Wireless Communications and Image Processing Microcontroller configures all programmable hardware, performs system self-test and stores data for stand-alone configuration User-controlled power supply voltage selection and monitoring to support advanced prototyping components today and tomorrow ular low-skew ck circuits (8) Introduction Méthodologie de conception Board-edge I/O I/O cable connectors (20) with interleaved grounds provide flexible connection to target systems freehole” area routable pins a wide variety g components System Explorer MP3CF hardware Modular hard-wired buses for high-fanout bi-directional nets e Interconnect provides softerconnect and nostic probing ler configures ble hardware, m self-test and or stand-alone configuration The System Explorer MP3CF is optimized for prototyping DSP-based pipelined designs with moderate requirements for Explorer MP3CF hardware interconnectSystem between prototyping components. The MP3CF architecture provides 1 maximum performance prototypes System Explorer for MP3CF interconnect architecture orer MP3CF is optimized incorporating fixed-pin prototyping comDSP-based pipelined derate requirements for ponents such as CPUs, DSPs, memory ween prototyping compoF architecture provides cards, etc. Use the MP3CF for building mance for prototypes ed-pin prototyping comhigh-speed prototypes of wireless commuCPUs, DSPs, memory nication and digital-imaging applications. e MP3CF for building Méthodes communes Spécificité des ASICs Spécificité des FPGAs Le prototypage : FPGA vers ASIC Exemple de projet “multi-plateforme” : LEON System Explorer MP3CF interconnect architecture Board-edge I/O USER COMPONENT HOLES FPGA FPGA FPGA REGION #1 FPGA FPGA FPGA REGION #2 FPGA FPGA FPGA REGION #3 FPGA FPGA FPGA USER COMPONENT HOLES FPGA FPGA FPGA REGION #1 FPGA types of wireless commutal-imaging applications. One-to-one connections between FPIC® Device and component pins FPIC #1 FPGA FPGA REGION #2 FPGA FPGA 140 / FPGA 140 FPIC #2 One-to-one connections between FPIC® Device and component pins FPGA All component pins in a given region connect through one FPIC® device / 140 FPIC #2 140 Component pins in different regions connect through two FPIC® devices / 2 1 ASIC vs FPGA r algorithms 32by testing actual voice transmission “Nokia made a commitment to create real-time prototypes of Méthodologie de conception- Le prototypage : FPGA vers ASIC opted the Aptix solution because it provides a 2 1 33- ASIC vs FPGA S. Mancini Version 1.0.19 all its new mobile phone designs. Prototypes are the only way bug environment while maintaining our objective 3 7 LEON-2 User’s 9 voice transmission to validate our Manual algorithms by testing actual erification. FPIC #3 / GLOBAL INTERCONNECT LINES 1 bile phone designs. Prototypes are the only way 140 All component pins in a given region connect through one FPIC® device Component pins in different regions connect through two FPIC® devices / a commitment to create real-time prototypes of FPIC #1 FPIC #3 / GLOBAL INTERCONNECT LINES 140 Durcissement aux radiations SoC Bilan FPGA REGION #3 FPGA 5 s al Staff, Nokia (San Diego, CA) quality. We adopted the Aptix solution because it provides a productive debug environment while maintaining our objective 4 1.4 Functional overview Architecture de LEON 3 6 of real-time verification. 7 A block diagram of LEON-2 can be seen in figure 1. Member of Technical Staff, ASIC Engineering, Nokia (San Diego, LEON CA) processor Local ram FPU 4 Integer unit Debug Support Unit PCI CP I-Cache D-Cache Local ram 8 Ethernet MMU AMBA AHB Debug Serial Link Cibles technologiques 5 Stelios Podimatis Timers Memory Controller AHB Controller IrqCtrl UARTS I/O port AHB/APB Bridge AMBA APB 8/16/32-bits memory bus PROM I/O SRAM 6 Technologie Modèle comportemental Xilinx VIRTEX/2 FPGA Atmel ATC18/25/35 UMC FS90A/B UMC 0.18 um CMOS TSMC 0.25 um w. Artisan rams Actel Proasic FPGA Actel AX anti-fuse FPGA RAM inférée instanciée instanciée instanciée instanciée instanciée instanciée instanciée PADS inférés inférés instanciés instanciés instanciés instanciés inférés inférés SDRAM Références : http ://www.gaisler.com 1 Figure 1: LEON-2 block diagram 34- ASIC vs FPGA Méthodologie de conception- Exemple de projet “multi-plateforme” : LEON 1.4.1 Integer unit S. Mancini The LEON integer unit implements the full SPARC V8 standard, including all multiply and divide instructions. The number of register windows is configurable within the limit of the SPARC standard (2 - 32), with a default setting of 8. To aid software debugging, up to four watchpoint registers can be configured. Each register can cause a trap on an arbitrary instruction or data address range. If the debug support unit is enabled, the watchpoints can be used to enter debug mode. 1.4.2 Floating-point unit and co-processor The LEON model does not include an FPU, but provides a direct interface to the Meiko FPU 35- ASIC vs FPGA Méthodologie de conception- Exemple de projet “multi-plateforme” : LEON S. Mancini Organisation du projet cache Exemple de code cachemem.vhd tech_map.vhd entity cachemem is entity syncram is ... ... dtags0 : syncram port map (... inf : if INFER_RAM generate ... u0 : generic_syncram generic map ( ... hb : if (not INFER_RAM) generate atc1 : if TARGET_TECH = atc18 generate u0 : atc18_dpram generic map (... ... virtex2_syncram RAMB16_S36 syncram proasic_syncram RAM256x9SST generic_syncram atc18_syncram Code VHDL hdss1_128x32cm4sw0 tech_act18.vhd – pragma translate_off entity hdss2_512x32cm4sw0 is ... architecture behavioral of hdss2_512x32cm4sw0 is ... – pragma translate_on Les mémoires instanciées sont à la fois : Des boîtes noires pour la synthèse Les entités sont considérées comme des cellules de la bibliothèque. Des descriptions comportementales pour la simulation Elles peuvent être fournies par le vendeur de RAM. 36- ASIC vs FPGA Méthodologie de conception- Exemple de projet “multi-plateforme” : LEON S. Mancini entity atc18_syncram is ... id0 : hdss1_128x32cm4sw port map (... ... 37- ASIC vs FPGA Durcissement aux radiations S. Mancini Single Event Upset (SEU) Plan Une particule peut faire changer d’état les éléments de mémorisation (Latch, registres, SRAM, . . . ) . Introduction Méthodologie de conception Durcissement aux radiations e gnd Durcissement des ASICs Durcissement des FPGAs N+ s Substrat N P P N vdd N P+ Caisson P SoC Bilan Select Select s 38- ASIC vs FPGA e 0 39- ASIC vs FPGA Durcissement aux radiations S. Mancini Single Event Transient (SET) Latchup La circuiterie combinatoire peut être altérée : Une erreur à l’instant d’échantillonnage peut être mémorisée L’arbre d’horloge génère des fronts parasites DQ gnd P+ Substrat P vdd N N P P N+ Caisson N Clk Clk D D Clk Q Q SET sur la donnée 40- ASIC vs FPGA Durcissement aux radiations SET sur l’horloge S. Mancini 41- ASIC vs FPGA Durcissement aux radiations S. Mancini Principales méthodes Plan Utilisation de technologies : Introduction Méthodologie de conception Durcissement aux radiations Sur-mesures Dissipation des charges (dimensionnement, capacités) Filtrage temporel (retard+vote) Isolation des transistors Cellules intra-redondantes Durcissement des ASICs Durcissement des FPGAs SoC Bilan Standards TMR Codes correcteurs d’erreur Auto-test 43- ASIC vs FPGA Durcissement aux radiations- Durcissement des ASICs 42- ASIC vs FPGA Les registres S. Mancini Les mémoires TMR : Triple Modular Redundancy SRAM Standard Des codes correcteurs d’erreurs protègent les données stockées. Des bits supplémentaires sont nécessaires. Spécifiques Les bits d’un mot sont spatialement séparés. La surface est accrue. Vote (S)DRAM CLK Les registres doivent être éloignés pour ne pas subir le même défaut. Il doivent être mis à jour par la valeur corrigée. 44- ASIC vs FPGA Durcissement aux radiations- Durcissement des ASICs S. Mancini Les SEU accélèrent la décharge des points mémoire. On peut accroître le taux de rafraîchissement. 45- ASIC vs FPGA Durcissement aux radiations- Durcissement des ASICs S. Mancini Introduire des technologies d’auto-test dans les circuits. Méthodologies de durcissement Méthodes automatiques Technologies spécifiques Les cellules durcies sont utilisées au lieu des cellules standards. Atmel propose ATC18RHA. la technologie durcie 0.18µ TMR la synthèse “classique” est suivie d’une modification de netlist. Cela peut être fait par des scripts des outils de synthèse ou par modification des fichiers résultats. Utilisation de gate-array durcis Par conception 46- ASIC vs FPGA Durcissement aux radiations- Durcissement des ASICs 49 S. Mancini Origine des disfonctionnements Plan Les éléments des FPGAs qui sont susceptibles de provoquer des disfonctionnements : Introduction Méthodologie de conception Durcissement aux radiations Registres des cellules RAM embarquée La configuration est sensible aux SEU Durcissement des ASICs Durcissement des FPGAs La SRAM peut être altérée (XC2VP125 : 43 Mbits de configuration) Les Anti-fusibles peuvent “claquer” Les EEPROM peuvent changer d’état SoC Bilan La logique générique génère des SET Logique d’interconnexion Arbre d’horloge 48- ASIC vs FPGA Durcissement aux radiations- Durcissement des FPGAs 47- ASIC vs FPGA S. Mancini Les éléments de configuration externe (pour les FPGAs de type SRAM) doivent aussi être protégés. Remèdes Les FPGAs sont plus délicats à durcir : Les registres et la RAM Ce sont les mêmes méthodes que les ASICs. La configuration Adopter des technologies moins sensibles aux SEUs Les anti-fusibles sont moins sensibles que les SRAM/EEPROM Vérifier la configuration Utilisation de la configuration partielle des FPGAs pour vérifier les cellules automatiquement. Insérer de l’auto-contrôle des calculs Insérer des séquences connues dans les calculs pour vérifier les résultats ROM de séquences et références LFSR Une détection de faute provoque la reconfiguration du FPGA. 49- ASIC vs FPGA Durcissement aux radiations- Durcissement des FPGAs 52 S. Mancini Composants spécifiques Méthodologie de durcissement Il est possible d’implanter des TMR de façon transparente. Pour les FPGAS d’Actel, Synplify permet d’implanter directement : Actel propose des circuits résistants aux radiations : Programmation par anti-fusibles résistants Sans registres R T 5 4 S X - S R a d To l e r a n t F PG A s f o r S p a c e A p p l i c a t i o n s To achieve the SEU requirements, the D flip-flop in the RT54SX-S R-cell is enhanced (Figure 3). Both the master and slave “latches” are actually implemented with three latches. The feedback path of each of the three latches is voted with the outputs of the other two latches. If one of the three latches is struck by an ion and starts to change state, the voting with the other two latches prevents the change from feeding back and permanently latching. Care was taken in the layout to ensure that a single ion strike could not affect more than one latch. Figure 4 is a simplified schematic of the test circuitry that has been added to test the functionality of all the components of the flip-flop. The inputs to each of the three latches are independently controllable so the voting circuitry in the feedback paths can be exhaustively tested. This testing is performed on an unprogrammed array during wafer sort, final test and post burn-in test. This test circuitry cannot be used to test the flip-flops once the device has been programmed. Les registres sont faits avec des éléments combinatoire des Flip-flop combinatoire des TMR des Flip-flop combinatoire avec TMR Avec des registres durcis Q D CLK CLK En VHDL, cela se fait à l’aide d’attributs : Voter Gate architecture top of top is attribute syn_radhardlevel of top : architecture is "tmr_cc" ; ... attribute syn_radhardlevel of counter_q : signal is "tmr" ; ... CLK CLK CLK CLK CLK CLK Les latchs sont séparées pour ne pas subir les mêmes rayonnements. Figure 3 • RT54SX-S R-Cell Implementation of D Flip-Flop Using Voter Gate Logic 1 Q D 50- ASIC vs FPGA Durcissement aux radiations- Durcissement des FPGAs S. Mancini 51- ASIC vs FPGA Durcissement aux radiations- Durcissement des FPGAs Tst1 Voter Gate Tst2 Tst3 Test Circuitry Figure 4 • R-Cell Implementation— Test Circuitry CLK S. Mancini Efficacité des durcissements Plan Quelques circuits d’Actel : LRH1280 0.8 µm ( A1280 ) Flip Flop Flip Flop (CC) TMR Introduction Méthodologie de conception Durcissement aux radiations SoC GEO SEU 10−6 10−7 10−10 RTAX 0.15 µm (AX 0.15 µm S-cell=TMR) Famille AX RTAX SRAM Registre LETTH GEO SEU LETTH GEO SEU 1, 4 3.10−7 3, 36 > .. > 2, 89 10−6 1, 4 10−10 (EDAC) > 37 < 10−10 Pas de SEL pour LET = 120 MeV-cm2/mg Rappels sur les SoCs Etude comparative Bilan LETTH en MeV-cm2/mg GEO SEU= erreur/bit/jour en orbite géostationnaire 52- ASIC vs FPGA SoC 53- ASIC vs FPGA S. Mancini Constituants des SoCs Un SoPC : Excalibur (Altera) Les technologies actuelles permettent de mettre sur un même circuit : ASIC Processeurs Mémoire (SRAM et DRAM) Bus systèmes Analogique SoC=System on Chip. Les circuit programmables permettent le même type de réalisation : les SoPC (System on Programmable Chip). 54- ASIC vs FPGA SoC- Rappels sur les SoCs S. Mancini 55- ASIC vs FPGA SoC- Rappels sur les SoCs S. Mancini Les microprocesseurs Plan Ils sont disponibles selon les besoins. Introduction Méthodologie de conception Durcissement aux radiations SoC ASIC Précaractérisés Optimisés par les fondeurs sous licence. Synthétisables Modèles disponibles de haut niveau pour la synthèse. Certaines parties doivent être adaptées à la technologies. Rappels sur les SoCs Etude comparative Bilan Paramétrables Les processeurs s’adaptent aux besoins de l’application : FPGA Taille et type des caches Mécanismes systèmes (TLB, adressage virtuel, . . . ) Co-processeurs Performances : MIPS 32 bits = 300 MHz 56- ASIC vs FPGA 57- ASIC vs FPGA SoC- Etude comparative S. Mancini Les microprocesseurs Les bus On trouve deux type de processeurs : Les technologies sont adaptées aux besoins. Synthétisables ASIC Modèles génériques (ex Leon) ou processeur fournis par vendeurs de FPGAs (ex : NIOS (Altera), MicroBlaze (Xilinx)). ASIC Esclave Esclave Esclave Esclave Esclave Esclave Ressources utilisées : RAM double port, CAM. Mux Performance ≈ 50 MHz La limitation des ressources impose des processeurs simples. Intégrés dans les FPGA Maître Maître Mux Mux Maître Maître Bus Trois-états Bus à multiplexeurs ExempleExcalibur ARM (Altera), Virtex II Pro (Xilinx) FPGA FPGA Performance ≈ 300 MH Leurs caractéristiques sont figées. et peuvent cohabiter dans un même circuit. 58- ASIC vs FPGA SoC- Etude comparative S. Mancini 59- ASIC vs FPGA SoC- Etude comparative Les bus S. Mancini La mémoire Avalon Bus Specification La technologie est imposée par les ressources Les bus trois-états sont peu recommandés (et même souvent impossibles). The Avalon bus module is generated automatically by the SOPC Builder, so that the system designer is spared the task of connecting the bus and peripherals together. The Avalon bus module is very rarely used as a discrete unit, because the SOPC Builder will almost always be used to automate the integration of processors and other Avalon bus peripherals into a system module. The designer’s view of the Avalon bus module usually is limited to the specific ports that relate to the connection of custom Avalon peripherals. ASIC Note that the Avalon bus module (an Avalon bus) is a unit of active logic that takes the place of passive, metal bus lines on a physical PCB. (See Example 2). In this context, the ports of the Avalon bus module could be thought of as the pin connections for all peripheral devices connected to a passive bus. The Avalon Bus Specification Reference Manual defines only the ports, logical behavior and signal sequencing that comprise the interface to the Avalon bus module. It does not specify any electrical or physical characteristics of a physical bus. Pour économiser la logique, l’arbitrage peut être fait au niveau de chaque esclave : les fils d’interconnexions Bus Avalon sontLes nombreux. CPUs embarqués imposent des bus sys- ASIC Figure 2. Avalon Bus Module Block Diagram - an example system FPGA 1 The Avalon bus module provides the following services to Avalon peripherals connected to the bus: 6 FPGA Altera Corporation tèmes. UMC propose des bibliothèque et générateurs de SRAM. http ://www.umc.com/english/design/b_1.asp 60- ASIC vs FPGA SoC- Etude comparative S. Mancini 61- ASIC vs FPGA SoC- Etude comparative La mémoire ASIC Les mémoires sont disponibles sous forme de blocs pré-caractérisés. ROM et RAM sont générées selon les besoins. Les technologies actuelles permettent la cohabitation de plusieurs types de mémoires (SRAM, SDRAM, associatives, . . . ). Les ROMs sont crées sur-mesures. Performances 0,13 µm : SRAM 1K x 16 access time = 1,1 ns S. Mancini Horloges multiples Les FPGAs fournissent des blocs de mémoire élémentaires (≈ 4 KOctets). Ils peuvent être assemblées pour former de grandes quantités. Les ROMs sont synthétisées en circuits combinatoires. Pas de SDRAMs. ASIC Les ASICs permettent des architectures de domaines d’horloges complexes. Des FIFOs asynchrones adaptées permettent les changements de domaines : les méta-stabilitées sont résolues. Chaque domaine d’horloge a son arbre d’horloge propre. Application-Specific SOC Multiprocessors CAB FPGA Xilinx XC2VP125 (Virtex II Pro) (0,13 µm ) 556 blocs de SRAM de 18Kbits = 10,008 Kbits Configurations ( Timings 62- ASIC vs FPGA SoC- Etude comparative 16K x 1 bit 8K x 2 bits SelectRAM CLB Setup 0,4 0,5 4K x 4 bits 2K x 9 bits Prop 1,5 1,8 ICP1 + ICP2 + MMI 1394 FPGA 1K x 18 bits 512 x 36 bits Clk min 1,3 1,4 S. Mancini MBS + VIP1 + VIP2 MPEG 63- ASIC vs FPGA SoC- Etude comparative Conditional access (MSP1 + MSP2) T-PI 82 horloges dans le PNX8500 (Philips). MSP3 M-PI TM32 chronously connected to the s another chiplet, we phase-aligne and analyzed the signal paths to constraints. We achieved clock tweaking the clock insertion dela ers in the clock module. Similarly clock trees as structurally identic As part of the physical design p design completion and manufact by implementing techniques such checks, antenna fixes, track filling of vias wherever possible. Figure 4 out plot for the Viper design’s init Table 3 summarizes the m parameters. PR3940 Figure 4. Layout of Viper (PNX8500). 1 Table 3. Design statistics. WE HAVE LEARNED much from th experience and trust it will gu future, particularly since the ne SOC designs are significantly m calling for still higher levels of inte of our current activities, in addit chip-development tasks, are inve efficient on-chip bus architectu design-reuse methodologies. S. Mancini Parameter Value Process technology TSMC 0.18 µm, six metal layers Transistors About 35 million Instances 1.2 million instances, or 8 million gates Acknowledgments Memories 243 instances, 750-Kbit memory CPUs 2 (TriMedia TM32 and MIPS PR3940) Peripherals 50 Clock domains 82 Clock speed TM32: 200 MHz; PR3940: 150 MHz; We thank the Viper manageme teams for their hard work, part architects Gert Slavenburg and L without whose foresight and lead ject never would have been succe SDRAM: 143 MHz Power 4.5 W Supply voltage 1.8-V core and 3.3-V I/O Package BGA456 References 1. S. Rathnam and G. Slavenburg, “A Overview of the Programmable M Processor, TM-1,’’ Proc. 41st IEE Society Int’l Conf. (COMPCON 96 chiplet timing, clock matching, and I/O timing analysis. Press, Los Alamitos, Calif., 1996, 2. D. Paret and C. Fenger, The I2C B & Sons, New York, 1997. Horloges multiples L’analogique R Functional Description: FPGA plexer buffer can also be driven by local interconnects. The DCM has clock output(s) that can be connected to global clock multiplexer buffer inputs, as shown in Figure 47. Each global clock multiplexer buffer can be driven either by the clock pad to distribute a clock directly to the device, or by the Digital Clock Manager (DCM), discussed in Digital Clock Manager (DCM), page 40. Each global clock multi- les arbres d’horloge sont déjà construits. Le nombre d’horloges est limité. Clock Pad CLKIN Clock Pad Local Interconnect DCM CLKOUT Les changements de domaines sont délicats. Clock Multiplexer ASIC I Clock Buffer ASIC O Clock Distribution DS083-2_43_122001 Figure 47: Virtex-II Pro Clock Multiplexer Buffer Configuration Global clock buffers are used to distribute the clock to some or all synchronous logic elements (such as registers in CLBs and IOBs, and SelectRAM+ blocks. macro bloc Apex 20k FPGA Xilinx propose des Digital Clock Manager Eight global clocks can be used in each quadrant of the Virtex-II Pro device. Designers should consider the clock distribution detail of the device prior to pin-locking and floorplanning. (See the Virtex-II Pro Platform FPGA User Guide.) les FIFOs asynchrones sont faites de cellules du FPGA : leur performances sont limitées. Figure 48 shows clock distribution in Virtex-II Pro devices. In each quadrant, up to eight clocks are organized in clock rows. A clock row supports up to 16 CLB rows (eight up and eight down). To reduce power consumption, any unused clock branches remain static. 8 BUFGMUX NE NW NW 8 BUFGMUX NE 8 8 8 max 16 Clocks 16 Clocks 8 SW 8 BUFGMUX SE 8 SE SW 8 BUFGMUX FPGA DS083-2_45_122001 Figure 48: Virtex-II Pro Clock Distribution 1 38 Horloges Virtex II Pro www.xilinx.com 1-800-255-7778 DS083-2 (v2.7) June 2, 2003 Advance Product Specification 64- ASIC vs FPGA SoC- Etude comparative S. Mancini L’analogique ASIC La plupart des technologies numériques sont compatibles avec l’analogique. Les blocs analogiques sont conçus à part et intégrés à l’assemblage. Les zones numériques/analogiques sont séparées pour réduire le bruit d’horloge. 65- ASIC vs FPGA SoC- Etude comparative S. Mancini Plan Pas d’analogique intégrée. Les circuit analogiques programmables existent mais ils sont peu performants. Introduction Méthodologie de conception Durcissement aux radiations SoC Bilan FPGA 67- ASIC vs FPGA 66- ASIC vs FPGA Bilan S. Mancini Comparaisons de performances Bilan Performances et complexité de la réalisation du microprocesseur LEON pour différentes cibles technologiques : Technologie Complexité Maîtrise complète du projet Fréquence ASIC Atmel 0.18 CMOS std-cell Atmel 0.25 CMOS std-cell UMC 0.25 CMOS std-cell Atmel 0.35 CMOS std-cell 35K gates + RAM 33K gates + RAM 35K gates + RAM 2 mm2 + RAM ASIC 165 MHz (pre-layout) 140 MHz (pre-layout) 130 MHz (pre-layout) 65 MHz (pre-layout)) Maîtrise de la résistance aux radiations Coûts réduits à grande échelle Fort taux d’intégration Performances maximum FPGA Xilinx XC2V500-6 (0.15 µm ) Altera 20K200C-7 (0.15 µm ) Actel AX1000-3 (0.15 µm ) 4,800 LUT + 14/32 block RAM 5,700 LCELLs + EAB RAM (52%) 7,600 cells + 14/36 RAM 65 MHz (post-layout) 49 MHz (post-layout) 48 MHz (post-layout) FPGA http ://www.gaisler.com/ 68- ASIC vs FPGA Bilan Les erreurs coûtent cher Connaissance approfondie de la technologie NRE S. Mancini 69- ASIC vs FPGA Bilan S. Mancini Bilan Conclusion Choisir entre un FPGA et un ASIC ? Temps de développement réduits ASIC FPGA Familles résistantes aux radiations Investissements réduits Contraintes d’architecture Méconnaissance des détails internes /caractéristiques Surface/coût Efficacité Fonctionnalité Souplesse Technologie Puissance de calcul Relachement de l’attention Accroissement des risques de pannes ? Réutilisabilité Temps de développement Débits Coûts unitaires élevées Complexité limitée Architecture mémoire Consommation ... ça dépend ... Performances limitées 70- ASIC vs FPGA Bilan S. Mancini 71- ASIC vs FPGA Bilan S. Mancini ASIC vs FPGA Références S. Mancini Plan Détaillé Introduction Problématique ASICs Les familles Evolution des technologie FPGA Principe Technologies de programmation Actel (ProAsic) Actel (Axcelerator) Xilinx (Spartan 3/Virtex II) Altera (Apex/Stratix) Modèles de coûts Coûts des FPGAs Coût des ASICS Comparaison Les circuits multi-projets Méthodologie de conception Méthodes communes Flot de conception Spécificité des ASICs Synthèse directe 72- ASIC vs FPGA Bilan S. Mancini Composants "précaractérisés"-IP Le “Back-End” Méthodologies de durcissement Durcissement des FPGAs Spécificité des FPGAs Origine des disfonctionnements Remèdes Méthodologie de durcissement Composants spécifiques Efficacité des durcissements Modèles d’entrées Placement/routage Utilisation des ressources Le prototypage : FPGA vers ASIC Principe Exemple : Aptix SoC Rappels sur les SoCs Exemple de projet “multi-plateforme” : LEON Architecture de LEON Cibles technologiques Organisation du projet Exemple de code Constituants des SoCs Un SoPC : Excalibur (Altera) Etude comparative Les microprocesseurs Les bus La mémoire Horloges multiples L’analogique Durcissement aux radiations Single Event Upset (SEU) Single Event Transient (SET) Latchup Durcissement des ASICs Principales méthodes Les registres Les mémoires Bilan Comparaisons de performances Bilan Conclusion Références
