Download Performance Analysis of Various Keeper Circuits By Using Carbon

International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 8 (2016) pp 5915-5919
© Research India Publications. http://www.ripublication.com
Performance Analysis of Various Keeper Circuits By Using Carbon
Nanotube Field Effect Transistor
Kishore Kumar. P. C
Department of Electronics and Communication Engineering,
Vels University, Chennai. India
Sathish Kumar. P
Department of Electronics and Communication Engineering,
Vels University, Chennai. India
To avoid performance degradation is to maintain Vth and Vdd
in similar scaling down process. Even though, this technique
increases the sub-threshold leakage current exponentially.
For continue scaling alternative material and devices are
needed in CMOS technology. The main problem in
conventional Si-MOSFET is minimisation of device with
multiple parameter like short channel effect, subthreshold
leakage current [11]-[17]. Higher carrier mobility in carbon
nanotube MOSFET(CN-MOSFET) are compared with
conventional Si-MOSFET [12]-[16]. Active current in a CNMOSFET are similar due to the replica physical dimensions of
N-channel and P-channel[12]-[15]. The leakage power are
reduce in six transistor CN-MOSFET compared with
conventional Si-MOSFET technology [18]-[20].
This paper is organized as follows. Device profiles of highperformance complementary CN-MOSFETs with 32-nm
channel length that are used for various keeper circuit are
introduce in Section II. The previously published different SIMOSFET keeper circuit are reviewed in Section III. The
novel CN-MOSFET keeper circuits is introduced and the
carbon nanotube circuits results and discussion are
characterized in Section IV. Conclusions V. future work are
offered in Section VI.
Abstract
In this paper, first time using CNTFET for designing a keeper
circuit instead of using MOSFET. This paper analysis about
performance of various keeper circuits using Stanford carbon
nanotube MOSFET 32 nanometer technology. Simulation
results of wide fan in gates designed using 32nm technology
and compared for 8, 16, 32 and 64bits input. According to our
research Keeper circuits are best adapted for CNTFET
technology.
Keywords: CNTFET 32nm Model, Keeper circuit
INTRODUCTION:
In this paper we are replacing all the existing technique and
proposed ckt model by using SandfordCNFET. Instead of
using bulk silicon in mosfet structure a single carbon nanotube
or an array of carbon nanotube as the channel material utilizes
in the CNFET which refers to the field effect transistor model
using carbon nanotube.
By comparing the performance of cntfet and mosfet it shows
different characteristics. PCNFET produces approximately
equal to 1500A/m of the on-current per unit width at a gate
which is driving by the voltage of 0. 6v. on the other hand,
PMOSFET produces approximately equal to 500A/m at the
same voltage. From the high gate capacitance and the
improved channel transport the advantage of ON-current has
been established. By comparing the gate capacitance per unit
width of the PMOSFET is lesser in twice that of CNFET. Due
to the effective gate capacitance of cntfet the compatibility
with high-k gate dielectrics becomes an advantage for
CNTFET. Due to the increasing mobility and band structure,
the carrier velocity cntfet is twice higher than the mosfet.
CNFET has four times higher transconductance.
In general WIDE Fan-in structure are used in TCAM match
line, flash memories, register files and some peripheral
circuits. Main concern with Wide Fan-in gates is increase in
variability and magnitude of leakage current where all pull
down network are leaky and also if, one of the legs is in ON
condition. In most CMOS circuit dynamic power dominates
the total power dissipation. Voltage scaling is a technique to
reduce power dissipation but voltage scaling in deep
submicron technology will create reliability probems [9]
However voltage scaling will cause performance degradation.
32-nm
CARBON
NANOTUBE
TRANSISTOR
TECHNOLOGY
N-channel and P-channel CN-MOSFET physical parameter
are used in keeper design for 32-nm CMOS technology. The
compact HSPICE model of Standford university carbonnano
tube is used for study and analysis of keeper circuits[21][10].
The CN-MOSFET channel length is 32-nm (Lg= 32 nm) and
physical parameter is shown in [3]. The performance and area
of a CN-MOSFET is depend upon the pitch(s) and diameter
(dCN) are 5. 3nm and 0. 84nm respectively for better
performance. N-Channel and P-channel transistor has similar
CN-pitch and CN-diameter [14], [15].
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 8 (2016) pp 5915-5919
© Research India Publications. http://www.ripublication.com
performance. To avoid those limitations and trade-off various
domino circuits has been implemented in several names such
as conditional keeper domino(ckd), high speed domino(hsd),
leakage current replica (lcr), controlled keeper by current
comparison domino(ckccd) with in-built of efficient keeper
design. As already mentioned that large number of leaky
nmos transistors used in wide fan-in dynamic gates, the
performance is less.
Instead of using bulk silicon MOSFET structure a carbon
nanotube field effect transistor(CNFET) considered in this
paper which refers to the array of carbon nanotubes as the
channel material.
(a)
Figure 2: CKD [1].
The most applicable dynamic logic is conditional keeper
domino logic(ckd). In this circuit two keeper transistors are
employed. One is small keeper and another one is large keeper
transistor. This logic can be operated in both precharge phase
and evaluation phase. The conditional keeper domino has the
drawback of increasing delay of the inverters and the noise
immunity of the circuit has to be improved by Nand gate.
The current mirror circuit is added to the keeper circuit of the
standard less domino logic in leakage current replica keeper.
In mirror circuit the M1 transistor in diode configuration in
which the gate of the pmos transistor is connected to the drain.
Due to this, the potential voltage level of keeper of both gate
and drain of the pmos is maintained. The potential of drain of
keeper voltage is one and the same.
(b)
Figure 1: (a) 3D view of CNMOSFET(b)Top view of
CNMOSFET[ 8].
Substrate in CN-MOSFET is shared by n-channel and pchannel, which act as a secondary gate. Vsub is Vsub=VDD/2
equal to the half of the supply voltage is deployed to get high
N-channel and P-channel CN-MOSFET active current [12].
The physical gate width (Wg)is used to determine the total
area of the transistor[13]. By adjusting the number of tube(N)
CN-MOSFET form channel and achieve better strength [12].
Wg= s ∗(N−1) + dCN+ 2 ∗Wov
(1)
Where,
S is the uniform array pitch
N is the number of tubes in a CN-MOSFET
dCN is the uniform nanotube diameter
Wov is the overhang width of the gate from the edge of CN
array
LITERATURE REVIEW
Using wide fan-in dynamic gates there is a problems of
increase of power consumption and evaluation delay is
increased in the circuit. These problems may occur due to
large number of leaky nmos transistors connected to the
dynamic node.
To avoid such problems the number of pull down legs is
limited. Hence there is a trade-off between robustness and
Figure 3: LCR [2]
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 8 (2016) pp 5915-5919
© Research India Publications. http://www.ripublication.com
account of reducing the sub-threshold leakage reduction by
means of increasing the body effect of the evaluation
transistor. Operation, When clk is low, the precharge phase is
activated. The transistor M3 is ON and turns OFF the mirror
transistorM2 to prevent sorcircui current through the transistor
M2. If clk is high, when output goes high in the evaluation
phase, the footer node is precharged o zero. The transistor M4
is driven by he output to pull down the footer node. Due to
evaluation phase there is a prevention in any sort circuit
power consumption in the static inverter.
The main advantage of lcr keeper is reducing the power
consumption. When clk is low, precharge phase is operated
and all the inputs are low. In precharge phase, the dynamic
node is charged to vdd. The keeper transistor mk2 is turned on
when the output goes low and it acts as a short circuit
transistor. The tracking process takes place when the drain of
the mk1 transistor is directly connected to the dynamic node.
By the process of diode configuration the drain voltage of m1
is at a low level of dynamic node. The drain voltage of m1
goes high which in turn reduces the leakage current.
Figure 4: CKCCD [3]
The operation of ckccd involves the controlling of keeper
transistor by the current comparison domino mechanism. So,
the dynamic node is discharged hence the keeper transistor is
turned off to prevent the contention current between the
keeper transistor and the pull down network. Because of this
process the power andthe propogation delay will be reduced.
Operation: when clk is low the ckt is in precharge phase. ON
mode transistors are Mpre, Mkeeper, M8 and the OFF mode
transistors are M1 and M2. Then by the transistor of Mpre, the
voltage of the dynamic node is raised to high. When clk is
high, the evaluation phase is operated. Some of the transistors
going to the OFF mode which are named as precharge
transistor and M8. Two states are possible in accordance with
the mirror current in discharge current of the PDN. First State,
The remaining transistors may be ON or OFF depending upon
the inputs. The voltage node is discharged to zero when the
mirror current is larger than the PDN leakage current incase of
all inputs are in low level. Henceforth, the dynamic node
remains at high level due to the keeper transistor is turned
ON. Second State, The discharging current of PDN is larger
than the mirror current if at least one of the inputs is in high
level, which in turn gives up the voltage if the node remains at
high level. Therefore, it reduces the contention current by
turning OFF the keeper transistor.
The NCNFET is connected in a diode configuration in series
with the evaluation network of the domino circuit. The
stacking effect takes place in dfd which in turns decreases the
sub-threshold leakage current. In the evaluation phase some
voltage drop established across the diode footer due to leakage
of evaluation transistor. The gate-source voltage of the OFF
state evaluation transistor goes negative resulting an
exponential reduction in the sub-threshold leakage due to the
voltage drop. The voltage drop across the diode also in
Figure 5: DFD [4].
Figure 6: HSD [5]
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 8 (2016) pp 5915-5919
© Research India Publications. http://www.ripublication.com
It is the leakage tolerant domino circuit. Operation: when clk
is high, the evaluation phase is operated. The input element is
low at the beginning of the evaluation phase. The keeper
transistor MP2 is turn OFF, when the Pmos transistor MP3 is
turned ON. If the output node is high, the clk delay is also
high, the delay which occur after a delay equal to the delay of
the inverters. Because of this scenario the MN1 remains at
OFF state. And the keeper transistor MP2 is also remains in
the OFF state. The dynamic node is connected to the output
node through the inverter when the output is at low after the
delay of the inverters in evaluation phase. Because of this
process, the keeper transistor is turned ON to keep the
dynamic node strongly connected to vdd till the end of the
evaluation phase.
The capacitance of the dynamic node is large in wide fan-in
gate hence speed is decreased dramatically. Due to many
parallel leaky path in wide gate, the noise immunity of the
gate is also reduced. These problems can be resolved by
upsizing keeper transistor. Eventhough using upsizing
technique the power consumption and delay are increased due
to the large contention. So, these problems can be solved by
comparison stage in which the current of pull-up network is
compared with the worst case leakage current. This
comparison would be achieved through if pdn implements
logical function is separated from the keeper transistor.
Table1: Average power
Title
8 bit
16 bit
32 bit
64 bit
CKDCNT[1] 5.5829E-10 7.4598E-10 1.1222E-09 1.8751-09
LCRCNT[2] 4.0075E-10 5.8865E-10 9.6661E-10 1.7185E-09
CKCCD[3] 4.5895E-10 5.13121E-09 3.5297E-09 3.5031E-09
DFDCNT[4] 2.5358E-10 3.0761E-10 3.8488-10 4.9393E-10
HSDCNT[5] 5.1088E-06 5.1088E-06 5.1089E-06 5.1091E-06
DPDCNT[7] 5.4660E-10 7.3654E-10 1.1710E-09 1.8638E-09
In the DPD [Fig. 8], according to [7] each section consists of
four legs to obtain the best results. All inverters and keepers
of the sections are set to least size and the length of the
transistor MK.
RESULT & DISCUSSION:
The proposed circuit was simulated using HSPICE in the
high-performance 32-nm standford model for 8, 16, 32, 64 bit
gate [21] and the supply voltage used in the simulations is 0. 7
V, which operates in 1-GHz clock frequency. For the worst
case and heavy load due to the high fan-out, the output
capacitance load is set at 5 fF[6]. The table1 shows the
analysis of CKDCNT, LCRCNT, CKCCDCNT, DFDCNT,
HSDCNT, DPDCNT for various number of bits like8, 16, 32
and 64bits. During average power analysis HSDCNT
consume more power than remaining circuits, Even though it
has better speed than CKDCNT, LCRCNT, CKCCD,
DFDCNT and DPDCNT. For 8bit analysis LCRCNT,
CKCCDCNT, DFDCNT, DPDCNT has 28. 21%, 17. 79, 54.
57%and 2. 00% efficient respectively compared with
CKDCNT. For 16 bit analysis LCRCNT, CKCCDCNT,
DFDCNT, DPDCNT has 21. 09%, 85. 46%, 58. 76% and 1.
27% efficient respectively compared with CKDCNT.
Similarly above table shows the result for 32 and 64 bits.
CONCLUSION:
We have presented a Various Carbon nanotube FET keeper
technique aimed at improving the robustness of 32nm wide
dynamic circuits in the presence of the increasingly large
leakage currents. These circuits are improved and effectively
utilized by scaling down the supply voltage and technology.
Even though researcher not able to achieve better results in
Cmos in some extent, due to that aspect CN-MOSFET are
replaced to achieve better performance by the lower threshold
voltages. We compared various keeper circuits for wide fan in
circuits like 8bit, 16bits, 32bits and 64bits and simulated using
EDA tool in 32 nm technology. All results are shown in
table1.
Figure 7: CCD [6].
FUTURE WORK:
In future work we can implement our proposed CNTFET
keeper circuits in CAM, TCAM, Flash memory, Registers etc.
According to our research it will give better performance and
efficiency in wide fan-in gates compared to using MOSFET.
After implementing the CNTFET keeper circuit in registers.
In future, have to employ in processor of computer’s control
unit.
Figure 8: DPD [7].
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International Journal of Applied Engineering Research ISSN 0973-4562 Volume 11, Number 8 (2016) pp 5915-5919
© Research India Publications. http://www.ripublication.com
REFERENCES:
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
[15]
A. Alvandpour, R. Krishnamurthy, K. Sourrty, and S.
Y. Borkar, “A sub 130nm conditional-keeper
technique, ” IEEE J. Solid-State Circuits, vol. 37, no.
5, pp. 633-638, May 2002.
Y. Lih, N. Tzartzanis, and W. W. Walker, “A
leakage current replica keeper for dynamic circuits, ”
IEEE J. Solid-State Circuits, vol. 42, no. 1, pp. 4855, Jan. 2007.
A. Peiravi and M. Asyaei, “Robust low leakage
controlled keeper by current-comparison domino for
wide fan-in gates, integration, ” VLSI J., vol. 45, no.
1, pp. 22-32, 2012.
H. Mahmoodi and K. Roy, “Diode-footed domino: A
leakage-tolerant high fan-in dynamic circuit design
style, ” IEEE Trans. Circuits Syst. I, Reg. Papers,
vol. 51, no. 3, pp. 495-503, Mar. 2004.
M. H. Anis, M. W. Allam, and M. I. Elmasry,
“Energy-efficient noise-tolerant dynamic styles for
scaled-down CMOS and MTCMOS technologies, ”
IEEE Trans. Very Large Scale (VLSI) Syst., vol. 10,
no. 2, pp. 71-78, Apr. 2002.
Ali Peiravi and Mohammad Asyaei” CurrentComparison-Based Domino: New Low-Leakage
High-Speed Domino Circuit for Wide Fan-In
Gates”IEEE Trans. Very Large Scale(VLSI) Syst.,
vol. 21, no. 5, pp. 934-943, May. 2013.
H. Suzuki, C. H. Kim, and K. Roy, “Fast tag
comparator using diode partitioned domino for 64-bit
microprocessors, ” IEEE Trans. Circuits Syst., vol.
54, no. 2, pp. 322-328, Feb. 2007.
Yanan Sun, HailongJiao and VolkanKursun” A
Novel Robust and Low-Leakage SRAM Cell With
Nine Carbon Nanotube Transistors” IEEE
Transactions on very large scale integration (vlsi)
systems, vol. 23, no. 9, september 2015.
H. Iwai, “CMOS Technology—Year 2010 and
Beyond, ” IEEE J. Solid-State Circuits, vol. 34, pp.
357-366, Mar. 1999.
S. A. Tawfik and V. Kursun, “Low power and robust
7T dual-Vt SRAM circuit, ” in Proc. IEEE Int. Symp.
Circuits Syst., May 2008, pp. 1452-1455.
V. Kursun and E. G. Friedman, Multi-Voltage
CMOS Circuit Design. New York, NY, USA: Wiley,
2006.
Y. Sun and V. Kursun, “Carbon nanotubes blowing
new life into NP dynamic CMOS circuits, ” IEEE
Trans. Circuits Syst. I, Reg. Papers, vol. 61, no. 2,
pp. 420-428, Feb. 2014.
Y. Sun and V. Kursun, “N-type carbon-nanotube
MOSFET device profile optimization for very large
scale integration, ” Trans. Elect. Electron. Mater.,
vol. 12, no. 2, pp. 43-50, Apr. 2011.
Y. Sun and V. Kursun, “Uniform diameter and pitch
co-design of 16 nm n-type carbon nanotube channel
arrays for VLSI, ” in Proc. IEEE 3rd Asia Symp.
Quality Electron. Design, Jul. 2011, pp. 211-216.
[16]
[17]
[18]
[19]
[20]
Y. Sun and V. Kursun, “Uniform carbon nanotube
diameter and nanoarray pitch for VLSI of 16 nm Pchannel MOSFETs, ” in Proc. IEEE 19th Int. Conf.
VLSI Syst.-Chip (VLSI-SoC), Oct. 2011, pp. 226231.
H.-S. P. Wong and D. Akinwande, Carbon Nanotube
and Graphene Device Physics. Cambridge, U. K. :
Cambridge Univ. Press, 2011.
G. E. Moore, “Cramming more components onto
integrated circuits, ” Electronics, vol. 38, no. 8, pp.
114-117, Apr. 1965.
S. Lin, Y.-B. Kim, and F. Lombardi, “Design of a
CNTFET-based SRAM cell by dual-chirality
selection, ” IEEE Trans. Nanotechnol., vol. 9, no. 1,
pp. 30-37, Jan. 2010.
Z. Zhang, M. A. Turi, and J. G. Delgado-Frias,
“SRAM leakage in CMOS, FinFET and CNTFET
technologies: Leakage in 8T and 6T SRAM cells, ”
in Proc. ACM Great Lakes Symp. VLSI, May 2012,
pp. 267-270.
A. K. Kureshi and M. Hasan, “Performance
comparison of CNFET-and CMOS-based 6T SRAM
cell in deep submicron, ” Microelectron. J., vol. 40,
no. 6, pp. 979-982, Jun. 2009.
Authors
Kishore kumar. P. C. was born in Tamil nadu, India on April
29, 1989. He received the B. E. and M. E. degrees in
Electronics and Communication engineering and VLSI
DESIGN from Anna University, Chennai, in 2010 and 2012,
respectively. In 2012, he joined REC, Perambalur as assistant
professor. where he is currently working in VELS
UNIVERSITY as assistant professor. His research interests
include Low power VLSI, Memory design, SOC design, etc.,
SATHISH KUMAR. P received the B. E. degree in
electronics and communication engineering from the
Priyadharshini Engineering College, Vaniyambadi, Tamilnadu
India, in 2006, the M. Tech degree in VLSI from the
Sathyabama University, Chennai, in 2013, and pursuing the
Ph. D. degree in Biomedical signal process from the Vels
University at chennai. He has published over 2 papers in VLSI
and holds one patents. His research interests include
Embedded System, Low Power VLSI, Nano Technology, etc.,
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