Download JRC4558 (Y) LINEAR INTEGRATED CIRCUIT

JRC4558 (Y)
LINEAR INTEGRATED CIRCUIT
DUAL OPERATIONAL
AMPLIFIER
DESCRIPTION
The JRC4558 is a monolithic integrated circuit
designed for dual operational amplifier.
FEATURES
DIP-8
*No frequency compensation required.
*No latch-up
*Large commom mode and differential voltage range
*Parameter tracking over temperature range
*Gain and phase match between amplifiers
*Internally frequency compensated
*Low noise input transistors
SOP-8
BLOCK DIAGRAM
Vcc
IN(-)
1
8
Vcc
IN1(-)
2
7
OUT2
IN1(+)
3
6
IN2(-)
Vee
4
5
IN2(+)
OUT1
IN(+)
OUTPUT
Vee
ABSOLUTE MAXIMUM RATINGS
Characteristic
Symbol
Value
Vcc
± 16
V
VI(DIFF)
±16
V
Power Dissipation
PD
400
mW
Input Voltage
VI
±15
V
Operating Temperature
TOPR
0~+70
°C
Storage Temperature
TSTG
-65~+150
°C
Supply Voltage
Differential input voltage
ＳＵＭ　1
Unit
JRC4558
LINEAR INTEGRATED CIRCUIT
ELECTRICAL CHARACTERISTICS( Ta=25°C ,Vcc=15V,Vee=-15V)
Characteristic
Supply Current
Input offset voltage
Input offset current
Input bias current
Large signal voltage gain
Commom Mode Input Voltage
Range
Commom Mode Rejection Ratio
Supply Voltage Rejection Ratio
Output Voltage swing
Power Comsumption
Slew Rate
Rise Time
Overshoot
Symbol
Icc
VIO
IIO
IBIAS
Gv
VI(R)
Test Condition
Rs<10kΩ
CMRR
PSRR
Vo(p-p)
Pc
SR
TRIS
OS
Vo(p-p)=10V,RL<2kΩ
20
±12
Rs<10kΩ
Rs<10kΩ
RL>10kΩ
70
76
Vi=10V,RL>2kΩ,CL<100pF
Vi=20mV,RL>2kΩCL<100pF
Vi=20mV,RL>2kΩ,CL<100pF
1.2
TYPICAL PERFORMANCE CHARACTERISTICS
Fig.1 Positive output voltage swing vs Load
resistance
15.0
Min
Typ.
3.5
2
5
30
200
±13
90
90
±12
70
Max
5.6
6
200
500
Unit
mA
mV
nA
nA
V/mV
V
dB
dB
V
mV
V/µs
µs
%
±14
170
0.3
15
Fig.2 Positive output voltage swing vs Load
resistance
13.0
Output Voltage (peak)
(V)
Output Voltage (peak)
(V)
11.0
9.0
7.0
5.0
3.0
1.0
10
2
10
3
10
4
10
5
10
Load resistance (Ω)
2
10
10
4
10
5
load resistance (Ω)
Fig.3 Power bandwith(large signal
swing vs frequency)
32.0
28.0
Output Voltage (V)
24.0
20.0
16.0
12.0
8.0
4.0
0
10
10
2
10
3
10
4
10
5
10
6
Frequency (Hz)
ＳＵＭ　2
JRC4558
LINEAR INTEGRATED CIRCUIT
Fig. 4 Burst Noise vs Rs
10
Fig. 5 RMS Noise vs Rs
3
10
2
2
Input Noise(RMS)
(µV)
Input Noise(peak)
(mV)
10
10
BW=1.0Hz To 1.0KHz
10
1
1
0.1
10
10
2
10
3
10
4
10
5
10
6
10
10
2
10
Rs (Ω)
3
10
4
10
5
10
6
Rs (Ω)
Fig. 6 Output Noise vs Rs
Fig. 7 Spectral Noise Density
140
10
120
Input Noise(nV/Hz)
Output Noise(RMS)
(mV)
Gv=1000
1
Gv=100
Gv=10
-1
10
100
Gv=10
Rs=100kΩ
80
60
40
20
Gv=1
-2
10
0
10
10
2
10
3
10
4
10
5
10
6
10
100
10
3
10
4
10
5
10
6
Frequency Hz)
Rs (Ω)
Fig. 8 Open loop frequency
response
Fig. 9 PHASE MARGIN vs
FREQUENCY
140
180
120
160
140
100
120
PHASE MARGIN
Avd ( dB)
80
60
40
20
0
100
80
60
40
20
-20
1
10
100
10
3
10
4
Frequency Hz)
10
5
10
6
10
7
0
1
10
100
10
3
10
ＳＵＭ　4
10
Frequency Hz)
3
5
10
6
10
7
JRC4558
LINEAR INTEGRATED CIRCUIT
PACKAGE DIMENSIONS
8-DIP-P-300
7.62
6.40
0.25
2.54
1.25
15
degree
3.30
5.08
3.40
9.20
0.46
8-SOP-P
5.72
3.95
6.00
0.41
1.27
5.13
1.95
4.92
ＳＵＭ　4